Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 PSW, EC mode format (continued)
machine-check mask 35
problem state bit 35
program-event recording (PER) mask 34
program mask 35
protection key 34
translation mode biv 34
wait state bit 35 PSW EMWP validity bit (in machine-check interruption code) 180 PSW (IPL) in absolute main storage 91 PSW mask and key validity bit (in machine-check interruption
code) 180 PSW translation control, bit 5 58 PURGE TLB (PTLB) instruction 107 R field of an instruction 20, 19
rate control 246
read backward command, I/O 218
READ DIRECT (RDD) instruction 107 real address (of a main-storage location) 57,96, 14
formation of 62
real-time clock, interval timer as a 49
receiver-check status bit 100 recognition of access exceptions 80 table 82
recovery
condition (machine-check interruption condition) 175
mechanisms 172
report mask (in control register 14) 182
system (machine-check interruption condition) 178,175
redundancy correction '172 reference and change recording (in main storage) 67
change bit 67, 38
reference bit 67, 38
references to storage
block concurrent 27
single access 26
region code
in machine-check extended interruption information 178
in machine-check interruption code validity bits 180 register
control 36
floating-point 16
general 16 20 save area (machine-check extended interruption
information) 178
validity bits (in machine-check interruption code) 180 remote operator control (ROCP) 248
repressible machine-check interruption condition
definition of 175
handling of (interruption action) 175
reset, ][/0 system 194,51
effect on working device 195
upon malfunction 195 RESET REFERENCE BIT (RRB) instruction 107 resets 50 CPU reset 51
initial CPU reset 51
initial program reset 52
manual initiation of 50 power-on reset 53
program reset 51
store status facility, effect on 54
system clear reset 53
324 System/370 Principles of Operation
restart
interruption 88
key 246
new PSW in main storage 91
old PSW in main storage 91
order 97
result
character in editing 151
condition in editing 151
retry, CPU 172
right of access to main storage 38 ROCP (remote operator control panel) 248
rounding (LRDR, LRER) instructions 166
RR instruction format 20 RS instruction format 20 running state 30 RX instruction format 20 S instruction format 20 save area (machine-check extended interruption information)
segment
index field 59
invalid bit 60 size bits (in control register 0) 59
table 59
table address (in control register 1) 59
table entry 59
table format 5? table length (in control register 1) 59
table lookup 61
translation exception 79
selective reset, I/O 195
selector channel 188
sense
command, I/O 219
data (in I/O) 219
order 97
sequence of main storage accesses (references) 23
sequence code 241
validity flag 241
sequential execution of instructions
change in by interruption 70 normal 22
serialization 28 SET CLOCK (SCK) instruction 108 SET CLOCK COMPARATOR (SCKC) instruction 108 SET CPU TIMER (SPT) instruction 109 SET PREFIX (SPX) instruction 109 SET PROGRAM MASK (SPM) instruction 138 SET PSW KEY FROM ADDRESS (SPKA) instruction 109 SET STORAGE KEY (SSK) instruction 110 SET SYSTEM MASK (SSM) instruction 110 set system mask suppression 32
shared main storage 95
shared sub channel 189 SHIFT AND ROUND DECIMAL (SRP) instruction 153
example 307 SHIFT LEFT DOUBLE (SLDA) instruction 138
example 302 SHIFT LEFT DOUBLE LOGICAL (SLDL) instruction 139 SHIFT LEFT SINGLE (SLA) instruction 139
example 302 SHIFT LEFT SINGLE LOGICAL (SLL) instruction 139 SHIFT RIGHT DOUBLE (SRDA) instruction 140 SHIFT RIGHT DOUBLE LOGICAL (SRDL) instruction 140 178

SHIFT RIGHT SINGLE (SRA) instruction 140 SHIFT RIGHT SINGLE LOGICAL (SRL) instruction 141
short block (in I/O) 233
short floating-point number 158 SI instruction format 20 sign and zone codes in decimal operands 147, 148
sign change in fixed-point operations 116
SIGNAL PROCESSOR (SIGP) instruction 110 signaling and response, CPU 97
orders 97
status bits 99
significance
exception 79
indicator in editing 151
simultaneous interruption requests, multiple (see priority of
interruptions) 89
skip (SKIP) flag (in CCW) 211
skipping (in I/O) 215 SLI (suppress-length-indication) flag in CCW 211
source digit in editing 150 source field (in limited channel logout) 240 source identification of interruptions 70 special operation exception 80 specification exception 77 SS instruction format 20 SSM suppression bit (in control register 0) 32 START I/O (SIO) instruction 204 START I/O FAST RELEASE (SIOF) instruction 204 start key 247
start order 97
states
check-stop 31 CPU 30 load 31
of I/O system 192
of time-of-day clock 46
operating 30 problem 30 program (see CPU states)
running 30 stopped 30 supervisor 30 wait 30 status
bits (signal processor) 99
conditions, I/O 229,237
in CSW 229, 237
modifier (I/O unit status condition) 229
of system (from wait, manual, and system indicators) 248
word, program (PSW) 32
stop-and-store-status order 98
stop key 247
stop order 97
stopped
state 30 status bit 99
storage
address wraparound 14
addressing, logical 58
alteration program event 42
control unit (SCU) identity (in limited channel logout) 240 key 38
logical validity (machine-check interruption code) 181
main (see main storage)
operand 20 Page of GA22-7000-4
Revised September 1, 1975
By TNL: GN22-0498
storage (con tinued)
operand reference (access) 25
validation 173
storage error
corrected bit (machine-check interruption code)
uncorrected bit (machine-check interruption code)
storage protection 38
accesses protected 39
action 38
fetch 38
key in storage 38
violation (see protection exception) STORE CPU ADDRESS (STAP) instruction 112 STORE PREFIX (STPX) instruction 113
store-status
facility 54
key 247
save area in absolute main storage 91 STORE (ST) instruction 141 STORE (STD, STE) instruction 168 STORE CHANNEL ID (STIDC) instruction 206 STORE CHARACTER (STC) instruction 141 180 180 STORE CHARACTERS UNDER MASK (STCM) instruction 141 STORE CLOCK (STCK) instruction 141 STORE CLOCK COMPARATOR (STCKC) instruction 111 STORE CONTROL (STCTL) instruction 111 STORE CPU ID (STIDP) instruction 112 STORE CPU TIMER (STPT) instruction 113 STORE HALFWORD (STH) instruction 142 STORE MULTIPLE (STM) instruction 142
example 302 store protection (see storage protection) 38
store reference, storage operand 25
store status 54 STORE THEN AND SYSTEM MASK (STNSM) instruction 113 STORE THEN OR SYSTEM MASK (STOSM) instruction 114
sub channel 188
non shared 189
not operational (I/O system state) 194
shared 189
working (I/O system state) 194
submask, external interruption 86 SUBTRACT (SR, S) instruction 143 SUBTRACT DECIMAL (SP) instruction 154 SUBTRACT HALFWORD (SH) instruction 143 SUBTRACT LOGICAL (SLR, SL) instruction 143 SUBTRACT NORMALIZED (SER, SE, SDR, SO) instruction 169 SUBTRACT NORMALIZED (SXR) instruction 169 SUBTRACT UNNORMALIZED (SWR, SW, SUR, SU) instruction 169
successful branching program event 42
supervisor-call interruption 84
supervisor-call interruption identification in main storage 90 SUPERVISOR CALL (SVC) instruction 144
supervisor program (see system program) 10 supervisor state 30 suppress-length-indication (SLI) flag in CCW 211
suppression, method of ending instruction execution 74
synchronization of TOD clock 101,47
synchronous machine check logout (see machine-check extended
logout and machine-check fixed logout)
synchronous MCEL control bit (in control register 14) 181
system
clear reset 53
console 243, 18
control 29
Index 325