The result of this operation replaces the former contents of
word 2. Word 2 now contains the original value of word 1.
Lastly, execution of the instruction
Machine Format Op Code L Bl Dl B2 02 Assembler Format OpCode 01 (L,B
1
),02(B
2
) XC 0(4,7),8(7)
produces the following result:
Word 1: 0000 0000 0000 0000 0000 0011 1001 00012 :=00 00 03 91
Word 2: 0000 0000 0000 0000 0001 0111 1001 00002 := 00 00 17 90 Result: 0000 0000 0000 0000 0001 0100 0000 00012 := 00 00 14 01 The result of this operation replaces the former contents of
word 1. Word 1 now contains the original value of word 2.
Notes:
1. With the XC instruction, fields up to 256 bytes in length
can be exchanged.
2. With the XR the contents of two registers
can be exchanged.
3. Because the X instruction operates storage-to-register
only, an exchange cannot be made solely by the use of
x.
4. A field EXCLUSIVE ORed with itself is cleared to zeros.
Execute (EX)
The EXECUTE instruction causes one instruction in main
storage to be executed out of sequence without actually
branching to the object instruction. EXECUTE may be
used to supply the length field for an SS instruction without
modifying the SS instruction in storage. For example, as­ sume that a MOVE (MVC) instruction is located at address 3820, with a fonnat as follows:
Machine Format Op Code L Bl Dl B2 02 Assembler Format OpCode Dl (L,B
1
),D2(B
2
) MVC 3(1,12),0(13)
where register 12 contains 00 00 89 13 and register 13
contains 00 00 90 AO. Further assume that at storage address 5000, the following EXECUTE instruction is located:
298 System/370 Principles of Operation
Machine Format
44 11 1 0 I A 000 A sse mbler Format Op Code R
1
, D2 (X
2
, B
2
)
EX 1,0(0,10) where register 10 contains 00 00 38 20 and register 1 con­ tains 00 OF FO 03. When the instruction at 5000 is executed, bits 24-31 of
register 1 are ORed with bits 8-15 of the instruction at 3820: Bits 8-15: 0000 00002 = 00 Bits 24-31: 0000 00112 = 03 Result: 0000 0011
2 = 03 causing the instruction at 3820 to be executed as if it orig­ inally were:
Machine Format Op Code L
D2 03 I C I Assembler Format Op Code Dl (L, B
1
), D2 (B
2
) MVC 3(4,12),0(13)
However, after execution:
Register 1 is unchanged 003 [he instruction at 3820 is l.lflchanged D 000 The contents of the four bytes starting atlocation 90AOhave been
moved to the four bytes starting at location 8916
The CPU next executes the instruction at address 5004 (PSW bits 40-63 contain 00 50 04) Load (L, LR)
The LOAD instructions place, unchanged, the contents of
a word in storage or of a register into another register. For
example, assume that the four bytes starting with location 21004 (a fullword boundary) are to be loaded into register 10. Initially:
Register 5 contains 00 02 00 00 Register 6 contains 00 00 10 04 The contents of register 10 are not significant
Storage locations 21004-21007 contain 00 00 AB CD
To load register 10, the RX form of the instruction can
be used:
Machine Format Op Code Rl X
2
B2 000 Assembler Format Op Code R
1
, D2 (X
2
, B
2
)
L 10,0(5,6)

After the instruction is executed, register 10 contains 00 00 AB CD.
Load Address (LA)
The LOAD ADDRESS instruction provides a convenient
way to place a nonnegative number 4095
1 0 in a register
without first defining the number as a constant and then
using it as an operand. For example, assume that the num­
ber 2048
10 is to be placed in register 1. One instruction
that will do this is:
Machine Format
41 11 1 0 1 0 800 Assembler Format Op Code R
1
• 02 (X
2
• 8
2
)
LA 1,2048(0,0) As indicated in the programming note in the instruction
description, the LOAD ADDRESS instruction can also be
used to increment a register by an amount 4095 1 0 speci­
fied in the D2 field. For example, assume that register 5
contains 00 12 34 56.
The instruction:
Machine Format Op Code R1 X
2
8
2
. OOA Assembler Format Op Code R
1
, 02 (X
2
, 8
2
)
LA 5,10(0,5)
adds 10 (decimal) to the contents of register 5 as follows:
Register 5 (old):
D2 field:
Register 5 (new): 00 12 34 56 00 00 00 OA 00 12 34 60 Load Halfword (LH)
The LOAD HALFWORD instruction places unchanged the
contents of a halfword in storage into the right half of a
register. The left half of the register is replaced by zeros or
ones to reflect the sign (leftmost bit) of the halfword.
For example, assume that the two bytes in storage loca­
tions 1802-1803 are to be loaded into register 6. Also
assume:
Register 6 contains 7F 12 34 56
Register 14 contains 00 00 18 02 Locations 1802-1803 contain 00 20 The instruction required to load the register is:
Machine Format Op Code R1 X
2
82
48 I 6 I 0 I E I 000 Assembler Format Op Code R
1
, 02 (X
2
, 8
2
)
LH 6,0(0,14)
After the instruction is executed, register 6 contains 00 00 00 20. If 1802-1803 contained a negative number,
for example, A 7 B6, the sign bit would again be propagated
to the left, giving FF FF A 7 B6 as the final result in regis­
ter 6.
Move (MVI) The MOVE (immediate) instruction can place one byte of
information from the instruction stream into any designated
location. For example, if the instruction
Machine Format Op Code 12 92 FA o 055 Assembler Format Op Code ° 1 (8
1
), 12 MVI 85(O),X'FA'
is executed, bits 8-15 of the instruction (1111 1010
2
) are
copied in storage location 85
10
. Move (MVC)
The MVC instruction can be used to move a data field from
one location to another. For example, assume that the fol­
lowing two fields are in storage:
Field 1 2048 2052 1 C1 I C2 I C3 I C4 I C5 I C61 C71 C81 C9 I CA I C8 I Field 2 3840 3848 I F1 I F21 F31 F41 F51 F61 F71 F81 F91 Also assume:
Register 1 contains 00 00 20 48
Register 2 contains 00 00 38 40 With the following instruction, the first eight bytes of
field 2 replace the first eight bytes of field 1:
Machine Format Op Code L 8
1
02 07 I I 000 000 Appendix I. Number Representation and Instruction-Use Examples 299