first CCV{ associated with an operation the PCI flag, either initially or upon command chaining,
the interruption may occur as early as immediately
upon the initiation of the operation. The PCI flag in
a CCW on data chaining causes the inter­
ruption to occur after all data designated by the pre­
ceding CCW has been transferred. The time of the
interruption, however, depends on the model and the
current a(:tivity in the system and may be delayed
even if the channel is not masked. No predictable
relation exists between the time the interruption due
to the PCI flag occurs and the progress of data
transfer to or from the area designated by the CCW, but the fields within the CSW pertain to the same
instant of time.
If chaining occurs before the interruption due to
the PCI flag has taken place, the PCI condition is
carried over to the new CCW. This carryover occurs
both on data and command chaining and, in either
case, the condition is propagated through the trans­
fer in channel command. The PCI conditions are not
stacked; that is, if another CCW is fetched with a PCI flag before the interruption due to the PCI flag
of the previous CCW has occurred, only one inter­
ruption takes place.
A CS\V containing the PCI bit may be stored by
an interruption while the operation is still proceeding
or by an interruption, TEST I/O, or CLEAR I/O upon the termination of the operation. It cannot be
stored by TEST I/O while lthe subchannel is in the
working state.
When the CSW is stored by an interruption be­
fore the operation or chain of operations has been
concluded , the command address is eight higher
than the address of the current CCW, and the count
is unpredietable. All unit-status bits in the CSW are
zero. If the channel has detected any unusual condi­
tions, such as channel data check, program check, or
protection check by the time the interruption occurs,
the corresponding channel-status bit is on, although
the condition in the subchannel is not reset and is
indicated again upon the termination of the opera­
tion.
The presence of any unit-status bit in the CSW indicates that the operation or chain of operations
has been concluded. The CSW in this case has its
regular format with the PCI bit added.
However, when the interruption condition due to
the PCI flag has been delayed until the operation at
the subchamnel has been concluded, two interrup­
tions from the subchannel may still take place, with
the first interruption indicating and clearing the PCI condition alone, and the second providing the CSW associated with the ending status. Whether one or
two interruptions occur depends on the model and
216 System/370 Principles of Operation
on whether the PCI condition has been assigned the
highest priority for interruption at the time of con­
cluding. TEST I/O or CLEAR I/O addressed to the
device associated with an interruption condition in
the sub channel clears the PCI condition as well as
the one associated with the concluding.
The setting of the PCI flag is inspected in every CCW except those specifying transfer in channel,
where it is ignored. The PCI flag is also ignored
during initial program loading.
Programming Note
Since no unit-status bits are placed in the CSW asso­
ciated with the concluding of an operation of the
selector channel by HALT I/O or HALT DEVICE, the presence of a unit-status bit with the PCI bit is
not a necessary condition for the operation to be
concluded. When the selector channel contains the PCI bit at the time the operation is concluded by
HALT I/O or HALT DEVICE, the CSW associated
with the concluded operation is indistinguishable
from the CSW provided by an interruption during
execution of the operation.
Program-controlled interruption provides a means
of alerting the program of the progress of chaining
during an I/O operation. It permits programmed
dynamic main-storage allocation.
Channel Indirect Data Addressing Channel indirect data addressing (CIDA), a compan­
ion facility to dynamic address translation, provides
assistance in translating data addresses for I/O oper­
ations. It permits a single channel command word to
control the transmission of data that spans noncontig­
uous pages in real main storage. Channel indirect data addressing is specified by a
flag bit in the CCW which, when one, indicates that
the data address in the CCW is not used to directly
address data. Instead, the address points to a list of
words, called indirect-data-address words (IDAWs),
each of which contains an absolute address designat­
ing a data area within a 2,048-byte block of main
storage.
When the indirect data addressing bit in the CCW is one, bits 8-31 of the CCW specify the location of
the first indirect data address word (IDA W) to be
used for data transfer for the command. Additional
IDAWs, if needed for completing the data transfer
for the CCW, are in successive locations in storage.
The number of IDAWs required for a CCW is deter­
mined by the count field of the CCW and by the
data address in the initial IDAW. When, for exam­
ple, the CCW count field specifies 4,000 bytes and
the first IDA W specifies a location in the middle of a 2,048-byte block, three IDA Ws are required.

Each IDA W is used for the transfer of up to 2,048 bytes. The IDA W specified by the CCW can
designate any location. Data is then transferred, for
read, write, control, and sense commands, to or from
successively higher storage locations or, for a read
backward command, to successively lower storage
locations, until a 2,048-byte block boundary is
reached. The control of data transfer is then passed
to the next IDAW. The second and any subsequent
IDAWs must specify, depending on the command,
the first or last byte of a 2,048-byte block. Thus, for
read, write, control, and sense commands, these IDAVls will have zeros in bit positions 21-31. For a
read backward command, these IDAWs will have
ones in bit positions 21-31. EX1;ept for the unique restrictions on the specifi­
cation of the data address by the IDA W, all other
rules for the data address, such as for protected stor­
age and invalid addresses, and the rules for data
prefetching, remain the same as when indirect data
addressing is not used.
A channel may prefetch any of the IDAWs per­
taining to the current CCW. An IDAW takes control
of the data transfer when the last byte has been
transferred for the previous IDAW for that CCW.
Errors detected in prefetched IDAWs are not indi­
cated until the IDA W takes control of the data
transfer.
Name Code
Write MMMM MM01 CD CC Read MMMM MM10 CD CC Read Backward MMMM 1100 CD CC Control MMMM MM11 CD CC Sense MMMM 0100 CD CC Transfer In Channel XXXX 1000 Explanation: CD Chain data CC Chain command SLI Suppress length indication SKIP Skip PCI Program-controlled interruption I DA Indirect data addressing
M Modifier bit
X Ignored Channel Command Codes SLI SLI SLI SLI SLI The format of the IDA Wand the significance of
its fields are as follows: 1000000001 Data Address
o 8 31
Bit positions 0-7 are reserved for future use and
must contain zeros. If any of the bits is detected to
be a one, a program-check status condition is gener­
ated, and the operation is terminated.
Bits 8-31 specify the location of the first byte to
be used in the data transfer. In the first IDAW for a
CCW, any location can be specified. For subsequent
IDAWs, depending on the command, either the first
or the last location of a 2,048-byte block located on
a 2,048-byte boundary must be specified. For read,
write, control, and sense commands, the beginning
of the block must be specified, and bits 21-31 of the
IDAW will be zeros. For a read backward command,
the end of the block must be specified, and bits 21-
31 of the IDA W will be ones. Improper data ad­
dress specification causes the program-check status
conditions to be generated and causes the operation
to be terminated.
Commands
The following table lists the command codes for the
six commands and indicates which flags are defined
for each command. The flags are ignored for all
commands for which they are not defined. Flags PCI IDA SKIP PCI IDA SKIP PCI IDA PCI IDA SKIP PCI IDA Input/ Output Operations 217