Assembler Format Op Code R
l
, D2 (X
2
, 8
2
)
AU 6,0(0,13)
is executed, the two numbers are added as follows: FPR6: 43 08 21 00 Guard
Digit
Shifted number from storage: 43 00 12 34 5
Sum: 43 08 33 34 5
The guard digit participates in the addition but is dis­ carded. The unnormalized sum replaces the high-order por­ tion of FPR6.
If the result in FPR6 is converted to a normalized number
(42 83 33 40 00 00 00 00) and is compared to the result in
FPR6 when ADD NORMALIZED was used (4283 3345 00 0000(0), it is apparent in this case that the use of ADD
NORMALIZED (with the retention of the guard digit) has
preserved some additional significance in the result. COmparE! (CE, CER, CD, CDR)
Assume that FPR4 contains 43 00000000000000 ( = 0), and FPR6 contains 34 12 34 56 78 9A BC DE (a positive
number). The contents of the two registers are to be com­ pared with the following long-precision instruction:
Machine Format Op Code Rl R2 Assembler Format Op Code R
l
, R2 CDR 4,6
When this instruction is executed, the number with the
smaller characteristic is taken from the register and right­ shifted until the two characteristics agree. The shifted con­ tents of FPR6 are 43 00000000000000, with a guard
digit of zero. Therefore, when the two numbers are com­ pared, condition code 0 is set, indicating an equality.
As the above example implies, when floating-point num­ bers are compared, more than two numbers may compare
equally if one of the numbers is unnormalized. For example,
the unnormalized floating-point number 41 00 1234 56 78
9A BC compares equally with all numbers of the form 3F
12 34 56 78 9A BC OX (X represents any hexadecimal num­ ber). When the COMPARE instruction is executed, the two
low-order digits are shifted right two places, the 0 becomes
the guard digit, and the X does not participate in the
comparison.
Note, however, that when two normalized floating-point
numbers are compared, the relationship between numbers
that compare equally is unique: each digit in one number
must be identical to the corresponding digit in the other
number. 310 System/370 Principles of Opera tion MULTIPROCESSING EXAMPLES
Compare and Swap (CS, CDS) The COMPARE AND SWAP and COMPARE DOUBLE AND
SWAP instructions can be used in multiprogramming or
multiprocessing environments to serialize access to counters,
control words, and other common storage areas.
Setting a Single Bit
In a multiprocessing system, two central processors have
access to the same main storage, and both can fetch, modify,
and store data in the same locations (such as in a system con­ trol block). In this configuration, if the OR (immediate) in­ struction is used to modify storage, such as when setting a
flag bit, program logic errors may occur.
Example of a Program Failure Using OR Immediate
Assume that two independently processing programs wish to
set different bits to one in a common byte in storage. The
following example shows how the use of the instruction OR immediate (01) can fail to accomplish this, if the programs
are executed nearly simultaneously on two different CPUs. One of the possible error situations is depicted.
Execution of Instruction 01 FLAGS,X'01' on CPU A
Fetch FLAGS X'OO' OR X'Ol' into X'OO' Store X'Ol' into FLAGS Execution of Instruction 01 FLAGS,X'80' on FLAGS CPU B X'OO' X'OO' X'OO' X'OO' X'80' X'Ol' Fetch FLAGS X'OO' OR X'80' into X'OO' Store X'80' into FLAGS FLAGS should have value of X'8l' following both updates.
The problem shown here is that the value stored by the 01 instruction executed on CPU A overlays the value that was
stored by CPU B. The X'80' flag bit was erroneously turned
off, and the program executing on CPU B now has invalid
data.
The COMPARE AND SWAP (CS) instruction is included
in System/370 to overcome this and similar problems. The CS instruction first checks the value of a storage location
and then modifies it only if it is the same as the program
expects; normally, this would be a previously fetched value.
If the location is not what the program expects, then the lo­ cation is not modified, but rather the current value of the
location is loaded into a general register, in preparation for
the program to loop back and try again. During the CS execution, no other CPU can access the subject storage
location.
The following instruction sequence shows how the CS in­ struction can be used to update a single bit in storage.
Assume that FLAGS is the first byte of a word in storage
called "WORD."

LA 6,X'80' Put bit to be ORed into register 6 SLL 6,24 Shift left 24 places to align the byte
to be ORed with the location of FLAGS within WORD L S,WORD Get original flag bit values
RETRY LR 4,5 Put flags to modify into register 4 OR 4,6 Turn on bit in new copy of flags CS S,4,WORD Store new flags unless original flags
were changed
BNE RETRY If new flags not stored, try again
The format of the CS instruction is:
Machine Format Op Code S1 BA ****
Assembler Format Op Code R
1
, R
3
, S1 CS 5,4,WORD
The CS instruction compares the first operand (register 5
containing the original flag values) to the second operand
(word) while storage access to the subject location is not
permitted to any CPU other than the one executing the CS instruction.
If the compare is successful, indicating that FLAGS still
has the same value that it originally had, the modified copy
in register 4 is stored into FLAGS. If FLAGS has changed
since it was loaded, the compare will not be successful, and
the current value of FLAGS is loaded into register S.
The CS instruction sets condition code 0 to indicate a
successful compare and swap, and condition code 1 to indi­ cate an unsuccessful compare and swap.
The program executing the example instructions tests the
condition code following the CS instruction and reexecutes
the flag-modifying instructions if the CS instruction indi­ cated an unsuccessful comparison. When the CS instruction
is successful, the program continues execution outside the
loop and FLAGS contains valid data.
Updating Counters
In this example, a 32-bit counter is updated by a program
using the CS instruction to ensure that the counter will be
correctly updated. The original value of the counter is ob­ tained by loading the word containing the counter into a
register. The original counter is then moved into another
register to provide a modifiable copy, and a register (con­ taining an increment to the counter) is added to the modi­ fiable copy to provide the updated tounter value. The CS instruction is then used to ensure a (-'".lid store of the
counter. The following instruction sequence performs this
procedure:
LA
L LOOP LR
AR
6,1
S,CNTR
4,5
4,6
Put increment (1) in register
Get original counter value Set up copy to modify Update counter in register CS 5,4,CNTR
BNE LOOP Page of GA22-7000-4 Revised September 1,1975
By TNL: GN22-0498 Update counter in storage
If original value changed, update new
value
CNTR (before): 00 00 00 10
CNTR (after): 00 00 00 11
The program updating the counter byte then checks the
result by examining the condition code. Condition code 0 indicates a successful update, and the program can proceed.
If the counter byte had been changed between the time that
the program loaded its original value and the time that it
executed the CS instruction, the CS instruction would have
loaded the new control byte value into register 5 and set
the condition code to 1, indicating an unsuccessful update.
The program would then have to update the new counter
value in register 5 and retry the CS instruction, retesting the
condition code, and retrying, until a successful update is
completed.
The following shows two CPUs, A and B, executing the
above program simultaneously. That is, both CPUs desire
to add one to CNTR. CPUA Reg4 Reg5
16 16
16 16
17 16
17 16 CPUB Comments
CNTR Reg4 Reg5
16
16
16
16
16
17
17
18
16
17
17
18
18
16
16 CPU A loads RegS and Reg4
from CNTR CPU B loads Reg5 and Reg4
from CNTR CPU B adds 1 to Reg4 CPU A adds 1 to Reg4 CPU A executes CS; successful
match store
17 CPU B executes CS; no match,
Reg5 changed
17 CPU B loads RegS into Reg4
and adds 1 to Reg4
17 CPU B executes CS; successful
match store
EXAMPLES OF THE USE OF COMPARE AND SWAP The following examples of the use of the COMPARE AND
SWAP instruction illustrate the applications for which the
instruction is intended. It is important to note that these
are examples of functions that can be performed by pro­ grams running enabled or by programs that are running on
a shared-main-storage multiprocessor. I Interlocked Sing1e-Word, or Smaller, Serially Reusable Resource (SR R)
The following routine allows a program to modify the con­ tents of a storage location while running enabled, even
though the possibility exists that another CPU may simul­ taneously update the same location and even though the
routine may be interrupted by another program that updates
the location.
Appendix I. Number Representation and Instruction-Use Examples 311