Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
The assignment of priority among requests for
interruption from channels is based on the type of
channel and its address assignment. The priorities of
channels 1-15 are in the order of their addresses,
with channel 1 having the highest priority. The inter­
ruption priority of multiplexer channel 0 is not fixed,
and depends on the model and on the current activi­
ty in the channel. Its priority may be above, below,
or between those of channels 1-15.
Intenuption Action
An I/O interruption can occur only when the chan­
nel the device is not masked and
after the execution of the current instruction in the CPU has been finished. If a channel has established
the priority among requests for interruption from
devices while the CPU was disabled for interruptions
from the channel, the interruption occurs immediate­
ly after the finishing of the instruction removing the
mask and before the next instruction is executed.
This interruption is associated with the highest prior­
ity condition on the channel. If interruptions are
allowed from more than one channel concurrently,
the interruption occurs from the channel having the
highest priority among those requesting interruption.
If the priority among interruption conditions has
not yet been established in the channel by the time
the interruption is allowed, the interruption does not
necessarily occur immediately after the finishing of
the instruction removing the mask. This delay can
occur regardless of how long the interruption condi­
tion has existed in the device or the subchannel.
The interruption causes the current program sta­
tus word (PSW) to be stored as the old PSW at loca­
tion 56 and causes the CSW associated with the intenuption to be stored at location 64. Subsequent­
ly, a new PSW is loaded from location 120, and
processing resumes in the state indicated by this PSW. The I/O device or, in the case of control-unit
end, the control unit causing the interruption is iden­
tified in BC mode by the channel address in bit posi­
tions 16-23 and by the device address in bit posi­
tions 24-31 of the old PSW. In EC mode, the I/O device or control unit is identified in the I/O-address field (locations 186-187) of the I/O communica­
tions area (IOCA). The CSW associated with the
interruption identifies the condition responsible for
the interruption and provides further details about
the progress of the operation and the status of the device. ProgJramming Note
When a number of I/O devices on a shared control
unit are concurrently executing operations such as
rewinding tape or positioning a disk-access mecha-
228 Systern/370 Principles of Operation nism, the initial device-end signals generated on
completion of the operations are provided in the
order of generation, unless command chaining is
specified for the operation last initiated. In the latter
case, the control unit provides the device-end signal
for the last initiated operation first, and the other
signals are delayed until the subchannel is freed.
Whenever interruptions due to the device-end signals
are delayed either because the channel is masked
or the subchannel is busy, the original order of
the signals is destroyed.
Channel Status Word
The channel status word (CSW) provides to the
program the status of an I/O device or the indica­
tion of the conditions under which an I/O operation
has been concluded. The CSW is formed, or parts of it-are replaced, in the process of I/O interruptions
and possibly during execution of START I/O, START I/O FAST RELEASE, TEST I/O, CLEAR I/O, HALT I/O, HALT DEVICE, and STORE CHANNEL ID. The CSW is placed in main storage
at reallocation 64 of the CPU to which the channel
is configured, and is available to the program at this
location until the time the next I/O interruption
occurs or until another I/O instruction causes its
contents to be replaced, whichever occurs first.
When the CSW is stored as a result of an I/O interruption, the I/O device is identified in BC mode
in the interruption code of the old PSW and in EC
mode in the I/O-address field of the I/O communi­
cations area (IOCA). The information placed in the CSW by START I/O, START I/O FAST RE­
LEASE, TEST I/O, CLEAR I/O, HALT I/O, or
HALT DEVICE pertains to the device addressed by
the instruction.
The CSW has the following for,mat: CCW Address
o 4 6 8 31 : I Unit Status I Channel Status I Count
32 40 48
The fields in the CSW are allocated as follows:
Protection Key: Bits 0-3 form the protection key
used in the chain of operations at the subchannel.
63
Logout Pending (L): Bit 5, when one, indicates that
an I/O instruction cannot be executed until a pend­
ing logout condition has been cleared. Bit 45, chan­
nel control check, will always be one when bit 5 is
one.

Defe"ed Condition Code (CC): Bits 6 and 7 indi­
cate whether conditions have been encountered sub­
sequent to the setting of a condition code 0 for
START I/O FAST RELEASE that would have
caused a different condition code setting for START I/O. The possible setting of these bits, and their
meanings, are as follows: Setting Of Bit 6
o
o
Bit 7
o
1
o
Meaning Normal I/O interruption
Deferred condition code is 1
(Reserved)
Deferred condition code is 3
CCW Address: Bits 8-31 form an absolute address
that is eight higher than the address of the last CCW
used.
Status: Bits 32-47 identify the conditions in the de­
vice and the channel that caused the storing of the
CSW. Bits 32-39, the unit status, are obtained over
the I/O interface and indicate conditions detected
by the device or the control unit. Bits 40-47, the
channel status, are provided by the channel and indi­
cate conditions associated with the subchannel. Each
of the 16 bits represents one type of condition, as
follows:
Bit Designation
32 Attention
33 Status modifier
34 Control unit end
35 Busy
36 Channel end
37 Device end
38 Unit check
39 Unit exception 40 Program-controlled interruption
41 I ncorrect length 42 Program check
43 Protection check
44 Channel data check
45 Channel control check
46 I nterface control check
47 Chaining check
Count: Bits 48-63 form the residual count for the
last CCW used.
Unit Status Conditions
The following conditions are detected by the I/O device or control unit and are indicated to the chan­
nel over the I/O interface. The timing and causes of
these conditions for each type of device are specified
in the SL or SRL publication for the device.
When the I/O device is accessible from more
than one channel, status due to channel-initiated
operations is signaled to the channel that initiated
the associated I/O operation. The handling of condi­
tions not associated with I/O operations, such as
attention or device end due to transition from the
not-ready to the ready state, depends on the type of
device and condition and is specified in the SL or
SRL publication for the device.
The channel does not modify the status bits re­
ceived from the I/O device. These bits appear in the
CSW as received over the interface.
Attention
Attention is generated when the device detects an
asynchronous condition that is significant to the
program. The condition is interpreted by the pro­
gram and is not associated with the initiation, execu­
tion, or concluding of an I/O operation.
The device can signal the attention condition to
the channel when no operation is in progress at the I/O device, control unit, or subchannel. Attention
can be indicated with device end upon completion of
an operation, and it can be presented to the channel
during the initiation of a new I/O operation. Other­ wise, the handling and presentation of the condition
to the channel depends on the type of device.
When the device signals attention during the initi­
ation of an operation, the operation is not initiated.
Attention accompanying device end causes com­
mand chaining to be suppressed.
Status Modifier
Status modifier is generated by the device when the
device cannot provide its current status in response
to TEST I/O, when the control unit is busy, when
the normal sequence of commands has to be modi­
fied, or when command retry is to be initiated.
When the status-modifier condition is signaled in
response to TEST I/O and the bit appears in the
CSW in the absence of any other status bit, presence
of the bit indicates that the device cannot execute
the instruction and has not provided its current sta­
tus. The interruption condition, which may be pend­
ing at the device or subchannel, has not been
cleared, and the CSW stored by TEST I/O contains
zeros in the key, command address, and count fields.
The 2702 Transmission Control is an example of a
type of device that cannot execute TEST I/O. When the status-modifier bit appears in the CSW
together with the busy bit, it indicates that the busy
condition pertains to the control unit associated with
the addressed I/O device. The control unit appears
busy when it is executing a type of operation that
precludes the acceptance and execution of any com-
Input/Output Operations 229