Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 Channel Subchannel A
A
2 3
A
2 2 3 2 2 3 Control Unit
or Device
A II I WIN I 1= 1*@ 1 *@ 3@ I A II I W IN I 1=1*@1*@ 3@
A I W
N
@ Available I:nterruption pending Working I\lot operational CSW stored When the SIOF function is performed, condition code 0 is set. The other condition code shown will be specified as a deferred condition code.
Note: Underscored condition codes pertain to
conditions that can occur only on the multiplexer channel. • When a nonimmediate I/O operation has been initiated,
and the channel is proceeding with its execution, condition
code 0 is set. • When an immediate operation has been initiated, and no
command chaining or command retry is taking place; or the
device is not ready; or an error condition has been detected
by the control unit or device, for the SIO function condition
code 1 is set, and the CSW is stored. For the SIOF function
condition code 0 is set, and a deferred condition code 1
interruption condition is generated.
Condition Codes Set by START I/O and START I/O FAST RELEASE Programming Notes
The advantage of START I/O FAST RELEASE
over START I/O is that less CPU time is required
for the execution of the instruction. For a START I/O instruction the device must be selected and
it must determine if the command and device condi­
tions allow the initiation of the operation prior to the
setting of the condition code, which allows the CPU to proceed to the next instruction. When the ST ART I/O FAST RELEASE instruction is used, the con­
dition code is set and the CPU proceeds to its next
instruction as soon as the control unit indicates it
is capable of communicating with the channel. Thus,
the CPU is freed for other activity earlier. A dis­
advantage, however, is that if a deferred condition
code is presented, the resultant CPU execution
time may be greater than that required in executing
START I/O. When the channel detects a programming error
during execution of the SIO function and the ad­
dressed device contains an interruption condition,
with the channel and sub channel in the available·
state, the instruction mayor may not clear the inter­
ruption condition, depending on the type of error
and the model. If the instruction has caused the de­
vice to be interrogated, as indicated by the presence
of the busy bit in the CSW, the interruption condi­
tion has been cleared, and the CSW contains pro­
gram or protection check, as well as the status from
the device.
Two major differences exist between START I/O and START I/O FAST RELEASE:
1. N onchained immediate commands on certain
channels (that is, those which execute START 206 System/370 Principles of Operation
1/ 0 FAST RELEASE independently of the
device) result in a condition code 0 for START I/O FAST RELEASE when the block­
multiplexing control bit is set to one, whereas
condition code 1 is set for START I/O. See
also programming note 2 following" Command Retry." 2. Condition code 0 is set by these certain chan­
nels for START I/O FAST RELEASE when
the block-multiplexing control bit is set to one,
even though the addressed device is not avail­
able or the command is rejected by the device.
The device information will be supplied by
means of an interruption.
Store Ch.annel 1D
STIDC [S] B203 o 16 20 Information identifying the designated channel is
stored in the four-byte field at location 168. STORE CHANNEL ID is executed only when
the CPU is in the supervisor state.
31
Bits 16-23 of the second-operand address identify
the channel to which the instruction applies. Bit posi­
tions 24-31 of the address are ignored.
The format of the information stored at location
168 is:

Channel Model Number
o 4
Maximum IOEL Length
31
Bits 0-3 specify the channel type. When a channel
can operate as more than one type, the code stored
identifies the channel type at the time the instruction
is executed. The following codes are assigned: 0000 Selector 0001 Byte multiplexer 0010 Block multiplexer
Bits 4-15 identify the channel model. When the
channel model is implied by the channel type and the CPU model, zeros are stored in the field.
Bits 16-31 contain the length in bytes of the long­
est I/O extended logout that can be stored by the
channel during an I/O interruption. If the channel
never stores logout information using the 10EL pointer, then this field is set to zero.
When the channel detects an equipment malfunc­
tion during the execution of STORE CHANNEL
ID, the channel causes the status portion, bits 32-47,
of the CSW to be replaced by a new set of status
bits. With the exception of the channel control check
bit (bit 45), which is stored as a one, all bits in the
status field are stored as zeros. The contents of the
other fields of the CSW are not changed.
When STORE CHANNEL ID cannot be execut­
ed because of a pending logout condition which af­
fects the operational capability of the channel, a full CSW is stored. The fields in the CSW are all set to
zero, with the exception of the logout-pending bit
and the channel control check bit, which are set to
ones. No channel logout is associated with this sta­
tus.
Program Exceptions:
Privileged operation
Resulting Condition Code:
o Channel ID correctly stored
1 CSW stored
2 Channel activity prohibited storing ID
3 Not operational
The condition code set by STORE CHANNEL
ID for all possible states of the I/O system is shown
graphically as follows. See "States of the
Input/ Output System" for a detailed definition of
the A, I, W, and N states.
A W N
Channel
o $ $ 3
A Available I Interruption pending
W Working
N
Not operational
$ When the channel is unable to store the channel 10 because
of its working state or because it contains a pending inter­ ruption condition, a condition code 2 is set. If the working
or interruption pending state does not preclude the storing
of the channel ID, a condition code 0 is set.
Condition Codes Set by STORE CHANNEL ID
Test Channel
TCH [S] 9FOO o 16 20 31
The condition code in the PSW is set to indicate the
state of the addressed channel. The state of the
channel is not affected, and no action is caused. Bits
8-15 of the instruction are ignored.
The instruction TEST CHANNEL is executed
only when the CPU is in the supervisor state.
Bits 16-23 of the second-operand address identify
the channel to which the instruction applies. Bit posi­
tions 24-31 of the address are ignored.
The instruction TEST CHANNEL inspects only
the state of the addressed channel. It tests whether
the channel is operating in the burst mode, is aware
of any outstanding interruption conditions from its
devices, or is not operational. When the channel is
operating in the burst mode and contains a pending
interruption condition, the condition code is set as
for operation in the burst mode. When none of these
conditions exist, the available state is indicated. No
device is selected and, on the multiplexer channel,
the sub channels are not interrogated.
Program Exceptions:
Privileged operation
Resulting Condition Code:
o Channel available
1 Interruption or logout condition pending in
channel
2 Channel operating in burst mode
3 Channel not operational
The condition code set by TEST CHANNEL for
all possible states of the addressed channel is shown
Input/Output Operations 207