FIELD1 (before): 00 01 23 45 67 8C
FIELD1 (after): 12 34 56 78 00 OC The second-operand address in this instruction specifies the
shift amount (three places) completely in the D2 field. The
rounding factor, 13, is not used in left shift, but it must be a
valid decimal digit.
Decimal Right Shift
In this example, the contents of storage location lFIELD2
are shifted one place to the right, effectively dividing the
contents of FIELD2 by 10 and discarding the remainder.
FIELD2 is five bytes in length. The following SRP instruc­ tion performs this operation:
Machine Format Ll 13 Sl 8
2 02 r---
F
-
O "---":"-4 ""-:;1 1-2 Op Code
Assembler Format SRP FIELD2(5),64 -1,0 FIELD2 (before): 01 23 45 67 8C
FIELD2 (after): 00 12 34 56 7C 0011 1111 6-bit two's
complement
for -1
The second-operand address specifies the shift amount
(one place)l completely in the D2 field. In the SRI' instruc­ tion, shifts to the right are specified by negative shift values,
which are represented as a six-bit value in two's-complement
form.
The six-bit two's complement of a number, n, can be rep­ resented as 64 -n. In this example, a right shift of one is
represented as 64 --I.
Decimal Right Shift and Round
In this example, the contents of storage location FIELD3
are shifted three places to the right and rounded, effectively
dividing by 1,000 and rounding to the nearest whole num­ ber. FIELD3 is four bytes in length.
Machine Format OpCode Ll 13 Sl 8
2 02 r----
F
- O """--3 --r-", -----T-5 -*-***--,---, I ClOG 1101 308 System/370 Principles of Operation Lr 6-bit two's
complement
for -:3
Assembler Format Op Code 51 (L
1
), S2' 13 SRP FIEL03(4),64 -3,5
FIELD3 (before): 12 39 60 OC FIELD3 (after): 00 01 24 OC The shift amount (three places) is specified in the D2 field.
The 13 field specifies the rounding of 5. the rounding
factor is added to the last digit shifted out (which is a 6) and
the carry, if any, is propagated to the left. Since 5 + 6 in
decimal totals one, plus a carry, a carry is propagated in the
above example, and, as a result, 1239.6 becomes 1240.
Multiplying by a Variable Power of 10 Since the shift value designated by the SRP instruction speci­ fies both the direction and amount of the shift, the operation
is equivalent to multiplying the decimal first-operand field
by 10 raised to the power specified by the shift value.
In this example, the SRP instruction is used to adjust a
decimal field by a variable scale factor contained in a general
register. Main storage location FIELD4 contains a decimal
integer (the decimal point is implied to be on the right).
FIELD4 is five bytes in length. Register 3 contains a fixed­ point binary value that is the scale factor of FIELD4 (the power of 10 by which FIELD4 is multiplied). The following
SRP instruction adjusts FIELD4 so that the implied decimal
point retains the two nearest decimal places (requiring the
implied decimal point to shift two places to the left, under
control of the D2 field)and multiplies FIELD4 by the vari­ able power of 10 contained in register 3:
Machine Format Op Code FO 4 I 5 **** 002 Assembler Format Op Code Sl (Li), 02 (8
2
), 13 SRP FI EL04(5),2(3),5
FIELD4 (before): 00 00 00 12 7C Case 1: Register 3 contains 00 00 00 00 If the scale factor is zero, FIELD4 represents
1 27 x 1 0° = 127
FIELD4 (after): 00 00 12 70 OC The implied decimal point is now shifted two places
to the left. Case 2: Register 3 contains 00 00 00 03 If the scale factor is 3, FIELD4 represents
127 x 10
3 = 127 000 FIELD4 (after): 01 27 00 00 OC The implied decimal point is now shifted two places
to the left.

Case 3: Register 3 contains FF FF FF FD
If the scale factor is -3, FIELD4 represents
127 x 10..,3 = 0.127 FIELD4 (after): 00 00 00 01 3C
The implied decimal point is now shifted two places
to the left; because the shift was to the righi.
FIELD4 is rounded to the nearest two deciinal
places.
In the preceding cases, the implied decimal is shifted two
places to the left, under control of the D2 field in the SRP instruction. The shifting is controlled by the address that is
resolved when the contents of the base register (GR 3) are
added to the displacement D2, effecting the multiplication
of FIELD4 by a variable power of 10. Zero and Add (ZAP)
Assume that the signed, packed-decimal field at storage lo­ cations 45004502 is to be moved to locations 4000-4004 with four leading zeros in the result field. Also assume:
Register 9 contains 00 00 40 00 Storage locations 4000-4004 contaIn 12 34 56 78 90 Storage locations 4500-4502 contain 38 46 OD After the instruction
Machine Format
F8 I 4 I 2 I 9 000 500 Assembler Format Op Code 01 (L1, 8,)' 02 (L2' 82) ZAP 0(5,9),X'500'(3,9) is executed, the storage locations 4000-4004 contain 0000 3846 OD; condition code 1 is set to indicate a negative re­ sult. Note that because the first operand is not checked for
valid sign and digit codes, it may contain any combination
of hexadecimal digits. FLOATING-POINT INSTRUCTIONS In this section, the abbreviations FPRO, FPR2, FPR4, and FPR6 stand for floating-point registers 0, 2,4, and 6,
respectively.
Add Normalized (AE, AER, AD, ADR)
The ADD NORMALIZED instructio.ns perform the addition
of two floating-point numbers and place the normalized re­ sult in a floating-point register. Neither of the two numbers
to be added must necessarily be normalized before addition
occurs. For example, assume that:
FPR6 contains 43 08 21 00 00 00 00 00 = 82.1
16 == approximately 130.06
10 Storage locations 2000-2007 contain 41 12 34 56 00 00 00 00 = 1.23456
16 == approximately 1.13
10 (normalized)
Register 13 contains 00 00 20 00 The instruction
Machine Format 000 Assembler Format Op Code R
1
, 02 (X
2
, 82)
AE 6,0(0,13) can be used to perform the short-precision addition of the
two operands. In this example, the instruction operates as
follows:
The characteristics of the two numbers are compared. Since the number in storage has a characteristic that is smaller
by 2, it is right-shifted after fetching until the characters
agree. The two numbers are then added:
FPR6: 43 08 21 00 Guard
Digit Shifted number from storage: 43 00 12 34 5
Intermediate sum: 43 08 33 34 5
Because the intermediate sum is unnorinaiized, it is left­ shifted to form the normalized floating-point number 42 83
33 45 (= 83.3345
16 = 131.2
10
), This number replaces the
high-order portion of FPR6. The low-order portion of FPR6 and the contents of storage locations 2000-2007 are
unchanged.
If the long-precision instruction AD is used, the result in FPR6 will be 42 83 33 45 600000 dO. Note that, in this
case, the use of the long-precision instruction provides one
additional hexadecimal digit of precision.
Add Unnormalized (AU, AUR, AW, AWR) The ADD UNNORMALIZED instructions operate identi­ cally to the ADD NORMALIZED instructions, except that
the final result is not normaHzed when ADD UNNORMAL­ IZED is used. For example, using the same operands as in
the example for ADD NORMALIZED, when the short­ precision instruction
Machine Format
7E I 6 I 0 I ° I 000 Appendix I. Number Representation and Instruction-Use Examples 309