Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 J?IFO UNLOCK Routine:
Initial conditions: PNTRS is the same location used in the FIFO LOCK routine. FUNLK L 1,PNTRS+4 GRI CONTAINS THE ADDRESS POST (1) OF THE PREVIOUS ELEMENT,
THAT IS, THE ELEMENT THAT WAS ADDED IN THE FLOCK ROUTINE. CONTINUE [ANY INSTRUCTION] Free-Pool-List Manipulation It is anticipated that a program will need to add and delete
items from a free list without using the lock/unlock routines.
This is especially likely since the lock/unlock routines re­ quire s.torage elements for queuing and may require working
storage. The lock/unlock routines discussed previously allow
simultaneous "lockers" but permit only one "'unlocker" at
a time. In such a situation, multiple additions and a single
deletion to the list may all occur simultaneously, but multi­ ple deletions cannot occur at the same time. In the case of
a chain of pointers containing free storage buffers, multiple
deletions along with additions can occur simultaneously. In
this case, the removal cannot be done using the CS instruc­ tion without a certain degree of exposure. Consider a chained list of the type used in the LIFO lock/
unlock example. Assume that the first two elements are at
locations A and B, respectively. If one program attempted
to remove the first element and was interrupted between
the fourth and fifth instructions of the LUNLK routine,
the list could be changed so that elements A and C are the
first two elements when the interrupted program resumes
execution. The CS instruction would then succeed in storing
the value B into the header, thereby destroying the list.
The probability of the occurrence of such list destruction
can be reduced to near zero by appending to the header a
counter that indicates the number of times elements have
been added to the list. The use of a 32-bit counter guaran­ tees that the list will not be destroyed unless the following
events occur, in this exact sequence:
1. An unlocker is interrupted between the fetch of the
pointer from the first element and the update of the
header.
2. The list is manipulated, including the deletion of the ele­ ment referenced in step 1, and exactly 2
32
- 1 additions
to the list are performed. Note that this takes on the
order of days to perform in any practical situation.
3. The element referenced in step 1 is added to the list.
4. The unlocker interrupted in step 1 resumes execution.
The routines ADD TO FREE LIST and DELETE FROM FREE LIST use such a counter in order to allow multiple,
simultaneous additions and removals at the head of a chain
of pointers.
The list consists of a doubleword header and a chain of
elements. The first word of the header contains a pointer
314 System/370 Principles of Operation
to the first element in the list. The second word of the
header contains a 32-bit counter indicating the number of
additions that have been made to the list. Each elemen t
contains a pointer to the next element in the list. A zero
value indicates the end of the list.
The following chart describes the free-pool-list manipu­ lation.
Function
ADD TO LIST (The incoming
element is at
location AI DELETE FROM LIST Action Hellder=O, Count Header=A, Count, Store the first word of the header into location A. Store the address A into the first word of the header.
Decrement the second word of the header by one.
The list is empty. Set the first word of the
header to the value of the
contents of location A.
Use element A.
The following routines allow enabled code to perform the
free-pool-list manipulation described in the chart.
ADD TO FREE LIST Routine:
Initial conditions:
GR2 contains the address of the element to be added.
GR4 contains the address of the header.
ADDQ LM 0,1,0(4) GRO,GRI = CONTENTS OF THE
TRYAGN ST LR
BCTR CDS BNE 0,0(2) 3,1 3,0 0,2,0(4 )
TRYAGN
HEADER POINT THE NEW ELEMENT TO THE TOP OF THE LIST MOVE THE COUNT TO GR3
DECREMENT THE COUNT UPDA TE THE HEADER
DELETE FROM FREE LIST Routine:
Initial conditions:
GR4 contains the address of the header.
DELETQ LM 2,3,0(4) GR2,GR3 = CONTENTS OF THE
HEADER
TR Y AGN L TR 2,2 IS THE LIST EMPTY? BZ EMPTY YES, GET HELP L 0,0(2) NO, GRO= THE POINTER FROM THE FIRST ELEMENT
LR 1,3 MOVE THE COUNT TO GRI CDS 2,0,0(4) UPDATE THE HEADER
BNE TRYAGN USE [ANY INSTRUCTION] THE ADDRESS OF THE REMOVED ELEMENT IS IN GR2
Note that the LM instructions at locations ADDQ and
DELETQ would have to be CDS instructions if it were not
for the rule that a doubleword fetch starting on a double­ word boundary must fetch the doubleword such that if
another CPU changes the doubleword being fetched, either I the entire new or the entire old value of the doubleword,
and not a combination of the two, is obtained.
Where more than one page-reference is given, major references
appear first.
absolute address 95, 14
absolute main storage 92
access control bits (in key in storage) 38
access exception 80 handling of (table) 81
priority of 83
recognition of 80 recognition of (table) 83
access to main storage, right of 38
accesses (references), sequence of main storage 23
active, state of address translation table entry 65
adapter, channel-to-channel 186
ADD (A, AR) instruction 117
ADD DECIMAL (AP) instruction 149
example 305 ADD HALFWORD (AH) instruction 117
example 291
ADD LOGICAL (AL, ALR) instruction 120 ADD NORMALIZED (ADR, AD, AER, AE) instruction 160 example 309 ADD NORMALIZED (AXR) instruction 160 ADD UNNORMALIZED (AWR, AW, AUR, AU) instruction 162
example 309 address
absolute 95, 14
base 21
branch 22
channel/device 192
failing-storage (see failing-storage address)
invalid 77
logical 14,58
of channel command word, in CSW 229
-real 95, 14, 57
translation (see dynamic address translation)
virtual 57
address arithmetic (generation) 21
address-compare controls 244
address generation 21
address identification, CPU 101 addresses
handling of 63
translated (see dynamic address translation)
types of 62
addressing
capability 14
information in a register 20 limitations of 14
main storage 14
wraparound 14
addressing exception 76,15
during address translation 61,62,81
summary table 77
. addressing, I/O channel 191
device 191
nonexistent or protected areas 213
Page ofGA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
alert condition (machine-check interruption) 175
degradation 179
warning 179
alteration mask for program-event recording 40 alteration of an instruction by EXECUTE 129
AND (NR, N, NI, NC) instruction 120 example 292 Index arithmetic (see decimal instructions; floating-point-instructions;
general instructions)
assembly language, symbolic operand designations for System/370 (see individual instruction descriptions)
assigned main storage locations 90 absolute 91
real 90 asynchronous fixed logout (see machine-check fixed logout)
asynchronous fixed logout control bit (in control register 14) 182
asynchronous machine-check logout (see machine-check extended
logout and machine-check fixed logout)
asynchronous MCEL control bit (in controlregister 14) 182
attached, state of address translation table entry 65
attachment of I/O devices 186
attention (I/O unit status condition) 229,239
availability, System/ 370 facilities for achieving 11
available (I/O system state) 193
B field of an instruction 20,21 backed-up bit (machine-check interruption code) 179
base address (in operand designation) 21
basic-control mode 31 PSW format 33
(see also extended-control mode)
BC mode (see basic-control mode)
binary notation, excess-64 159
bit, check 14
bits in a byte 14
block-concurrent references to storage 27
block of data, I/O definition 210 self-describing 214
block-multiplexer channel 188
block-multiplexing-control bit 189
block-multiplexing mode bit (in control register 0) 189
blocking of data (I/O operations) 210 boundaries in main storage, integral 15
branch address 22
BRANCH AND LINK (BAL, BALR) instruction 121
example 292
BRANCH ON CONDITION (BC, BCR) instruction 121
example 292
BRANCH ON COUNT (BCT, BCTR) instruction 122
example 293
BRANCH ON INDEX HIGH (BXH) instruction 122
example 293
BRANCH ON INDEX LOW OR EQUAL (BXLE) instruction 123
example 293
branch, successful (program event) 42
branching, general description of 22
burst mode 187
bus out check (sense data) 220 Index 315
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