Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 input/output (continued)
operations (continued)
conclusion of 222
initiation 210 termination by HALT I/O, HALT DEVICE 224
selective reset 195 system operation 189 reset 194, 51
input/output status condition 229, 239
input/output system states 192 INSERT CHARACTER (lC) instruction 130 INSERT CHARACTERS UNDER MASK (ICM) instruction 130 INSERT PSW KEY (IPK) instruction 104 INSERT STORAGE KEY (lSK) instruction 105 instruction
address in PSW BC mode 34
EC mode 35
validity bit 180 address, updated 22
address validity bit (machine-check interruption code) 180 B fidd 20 counter (instruction address portion of current PSW) 35
D field 20 decimal 147
exception handling, I/O 210 execution 22, 74
conceptual sequence (order) of 22
fetching 23
fetching program event 42 field, zero value in X or B 22
fixed-point (see general instructions)
floating-point 157
format 20 basic 20 I/O 197
general US I field 19
input/output 197
length code (ILC) in PSW in BC mode PSW 34
meaning 71 logical (see general instructions)
ope:rand 19
ope:ration 20 privileged 30 R field 19
sets and features 9
system controi i03 use examples 291
X field 20 instruction processing damage (machine-check interruption
condition) 178,175
instructions (see Appendix C for listings)
instructions
interruptible 73
offered by some models, but not listed in this manual 76
integral! boundaries in main storage 15
interface
address validity flag 241
control check, channel status condition 235 I/O 17 interlocked update storage reference 26
interlocks between logical and real storage references 63 interlocks between storage references 64
interpretation of order code, conditions precluding 98 320 :System/370 Principles of Operation
interrupt key 245, 86
interruption 86
mask bit (in control register 0) 86
priority of interruption 86
interruptible instructions 75
interruption (to program execution) 70 classes 70 clock comparator 47
code, BC mode PSW 34 CPU timer 48
enabling and disabling 70 external 84
general description 22
instruction length code use 71 I/O (input/output) 88
machine-check 75
new PSW 90,23 old PSW 90, 23
point of (machine check) 176
point of (occurrence of) 74
priorities 89
program 75
program-controlled 215
purpose 70 restart 88
source identification 70 supervisor-call 84
interruption action 70 machine check 175
table 72
interruption classes
external 84
input/output 88
machine check 75
program 75
supervisor-call 84
interruption, machine check 175
conditions 175
extended information 177
interruption code 178
interruption pending (I/O system state) 192
in channel 194
in device 193
in subchannel 194
interruptions, multiple PCI (see programming notes) 221
interval timer 49
external interruption 49,86
mask bit (in control register 0) 86
priority of interruption 86
updating 49
intervention required (sense data) 220 invalid address 76
invalid CBC
definition 172
handling of
in keys in storage 173
in registers 173
in storage 172
invalid (I/O programming) 234
invalid order status bit 100 I/O (see input/output) I/O interface 17 IOCA (input/output communications area) 240 10EL (input/output extended logout)
address in main storage 91

IOEL (input/output extended logout) (continued)
control register bit 182
pointer 240 IPL (initial program load) 54 IPL CCW1 , CCW2, in absolute main storage :91 IPL PSW in absolute main storage 91
key in storage error uncorrected bit (machine-check interruption
code) 180 key, protection, in CSW 228,236
key, storage 38
accesses 24
length of operand 19
immediate operands 20 register operands 20 storage operands 20 limited channel logout 240 detect field 240 field validity flags 241
in main storage 91 I/O address 242 I/O error alert 241
sequence code 241
source field 240 storage control unit (SCU) identity 240 type of termination 241
load
indicator 245
key 245
state 31
unit-address controls 246 LOAD (LDR, LD, LER, LE) instruction 165 LOAD (LR, L) instruction 1.30 example 298 LOAD ADDRESS (LA) instruction 131
example 299 LOAD AND TEST (LTDR, LTER) instruction 165 LOAD AND TEST (LTR) instruction 131 LOAD COMPLEMENT (LCDR, LCER) instruction 165 LOAD COMPLEMENT (LCR) instruction 131 LOAD CONTROL (LCTL), instruction 105 LOAD HALFWORD (LH) instruction 131
example 299 LOAD MULTIPLE (LM) instruction 132 LOAD NEGATIVE (LNDR, LNER) instruction 166 LOAD NEGATIVE (LNR) instruction 132 LOAD POSITIVE (LPDR, LPER) instruction 166 LOAD POSITIVE (LPR) instruction 132 LOAD PSW (LPSW) instruction 105 LOAD REAL ADDRESS (LRA) instruction 106 LOAD ROUNDED (LRDR, LRER) instruction 166
loading of initial program information 54
logical storage
address 14,58
address translation 58
addressing 58
logout
asynchronous/synchronous 177
extended/fixed 177
main storage, permanently· assigned locations 92
pending (LOP), in CSW 228
(see also machine-check extended logout and machine-check
fixed logout)
logout control 181 Page of GA22-7000-4 Revised September 1. 1975
By TNL: GN22-0498
long block (in I/O) 233
long floating-point number 158
machine-check
code 75, 178
detection 171
handling 172
machine-check control register
bits (chart) 183
subclass masks 182
subclass masks summary 183
machine-check extended interruption information 177
register save area 178
machine-check extended logout (MCEL)
address in control register 181
asynchronous, control of 182
asynchronous, definition 177
control, summary chart 183
length in machine-check interruption code 181
maximum length, in CPU ID 112
synchronous, control of 181
synchronous, definition 177
valid bit (machine-check interruption code) 180 machine-check fixed logout
area 177
asynchronous, control of 182
asynchronous, definition 177
control, summary chart 183
synchronous, definition 177
machine-check interruption 75
action 175
code 178
code in main storage 91
code validity bits 180 mask, BC mode 34
mask, EC mode 35
point of 176
machine-check logout, synchronous/asynchronous 177
control (chart) 183
extended (see machine-check extended logout)
fixed (see machine-check fixed logout)
machine-check mask
BC mode 34
EC mode 35
subclass masks 183
summary chart 183
machine-check save areas (machine-check extended interruption
information) 177
machine errors, handling of 172
main storage
accesses, sequence of 23
actual operation 23
conceptual operation 23
address wraparound 14
addressing 14
assigned locations 90 absolute 91
real 90 controlled sharing of by TEST and SET 144
controlled sharing of by COMPARE AND SWAP 123
general description 14
integral boundaries 15
power-on reset effect 53
reference and change recording 67
volatile 14
Index 321