The register pair 8-9 covers the second operand with bits
8-31 of register 8 containing the length of the second oper­
and, in this case 132 bytes. Bits 0-7 of register 9 contain
an EBCDIC blank character (X'40') to logically pad the
shorter operand. In this example, the blank padding char­
acter is used in the first operand, after the 100th character,
to compare with the remaining characters in the second
operand.
With the 4-5 and 8-9 register pairs thus set up, the format
of the CLCL instruction is:
Machine Format Op Code R1 R2 OF Assembler Format Op Code 1=l1' R2
CLCL 4,8 When thiis instruction is executed, the comparison starts
at the high-order end of both operands and proceeds to the
right. The operation ends as soon as an inequality is de­
tected or the end of the longest operand is reached.
If this ClLCL instruction is interrupted after 60 bytes are
successfully compared, the operand lengths in registers 5
and 9 are decremented to X'28' and X'48', respectively,
and the operand locations in registers 4 and 8 are incre­
mented to X'2083C' and X'20A3C'. When the CLCL instruction is reexecuted, the comparison begins at the
point of interruption.
If the instruction is interrupted after 110 bytes are suc­
cessfully compared, the operand lengths in registers 5 and
9 are decremented to 0 and X'16', respectively, and the
operand locations in registers 4 and 8 are incremented to
X'2086E' and X'20A6E'. . When the comparison ends, the condition code indicates
the result. The condition code settings are as follows:
Condition Code:
o Operands are equal, or both field lengths are
zero
2
3
First operand is low
First operand is high
When the operands are unequal, the address fields of regis­
ters 4 and 8 can be used to locate the bytes that caused the
mismatch. The byte count fields in registers 5 and 9 can be
used to determine how far the comparison progressed suc­
cessfully.
Convert to Binary (CVB)
The CONVERT TO BINARY instruction converts an eight­
byte, signed, packed-decimal number into a siglied binary
number and loads the result into a general register. After
296 System/370 Principles of Operation
the conversion operation is completed, the number is in the
proper form for use as an operand in fixed-point arithmetic.
For example, assume:
Storage locations 7608-760F contain a positive packed-decimal
number, 00 00 00 00 00 25 59 4C
The contents of register 7 are not significant
Register 13 contains 00 00 76 00 The format of the conversion instruction is:
Machine Format Op Code R1 X
2
8
2 008 Assembler Format Op Code R
1
, 02 (X
2
, 82)
CV8 7,8(0,13) After the instruction is executed, register 7 contains 00 00 63 FA = + 25,594 10 . Convert to Decimal (CVD)
The CONVERT TO DECIMAL instruction performs func­
tions exactly opposite to those of the CONVERT TO BINARY instruction. CVD converts a binary number in a
register to packed decimal and stores the result in a double­
word. For example, assume:
Register 1 contains 00 00 OF OF = 385510 Register 13 contains 00 00 76 00 PSW bit 12 = 0 (EBCDIC mode)
The format of the instruction is:
Machine Format Op Code R1 X
2
8
2 02 4E 11 1 0 I ° 008 Assembler Format Op Code R
1
, 02 (X
2
, 82) CVO 1,8(0,13) After the instruction is executed, locations 7608-760F contain 00 00 00 00 00 03 85 5C. The plus sign generated is the standard EBCDIC plus sign, 1100
2
• Divide (0, DR)
The DIVIDE instruction divides a dividend in an even/odd
register pair by the divisor in a register or in storage. Since the dividend is assumed to be 64 bits long, it is important
that the proper sign be first affixed. For example, assume
that:
Storage locations 3550-3553 contain 00 00 08 D7 = 227010 = the
dividend
Storage locations 3554-3557 contain 00 00 00 32 = 5010 = the
divisor

Register 6 does not contain all zeros
The initial contents of register 7 are not significant
Register 8 contains 00 00 35 50 The following assembly language statements load the reg­ isters properly and perform the divide operation:
Statement Comments
L 6,0(0,8) Places 00 00 08 07 into register 6 SROA 6,32(0) Shifts 00 00 08 07 into register 7
Register 6 is filled with zeros (sign bits)
° 6,4(0,8) Performs the division
The machine format of the preceding DIVIDE instruction
is:
Machine Format 004 After the foregoing instructions are executed:
Register 6 contains 00 00 00 14 = 20 1 0 = the remainder
Register 7 contains 00 00 00 2D = 4510 == the quotient
Note that if the dividend had not been first placed in regis­ ter 6 and shifted into register 7, register 6 would not have
been filled with the proper sign bits (zeros in this example),
and the DIVIDE instruction would not have given the
expected results. Exclusive OR (X, XR, XI, XC)
When the Boolean operation EXCLUSIVE OR is applied to
two bits, the result is one when one, and only one, of the
two bits is one; otherwise, the result is zero. When two
bytes are EXCLUSIVE ORed in System/370, each pair of
bits is handled separately; there is no connection from one
bit position to another.
Exclusive OR (XI) A frequent use of the EXCLUSIVE OR (XI) instruction is
to invert a bit (change a zero bit to a one or a one bit to a
zero). For example, assume that storage location 8082 contains 0110 1001
2
, To set the leftmost bit to one and
the rightmost bit to zero without affecting any of the other
bits, the following instruction can be used (assume that
register 9 contains 00 00 80 80): Machine Format Op Code 12 B1
97 81 9 002 Assembler Format Op Code 01 (81)' 12 XI 2(9),X'81'
When the instruction is executed, the byte in storage is EXCLUSIVE ORed with the immediate byte:
Location 8082: 0110 1001 2 Immediate byte: 1000 00012 Result: 1110 10002 The resulting byte with the leftmost and rightmost bits
inverted is stored in location 8082. Condition code 1 is
set.
Exclusive OR (XC)
The EXCLUSIVE OR (XC) instruction can be used to
change the contents of two areas in storage without the use
of an intermediate storage area. For example, assume that
two words are in storage:
Word 1 Word 2
358 35B 360 363 I 00 I 00 1
17
1
90 I 1 00 1 00 1141 01 I Execution of the instruction (assume that register 7 con­ tains 00 00 03 58):
Machine Format Op Code L
07 03 000 008 Assembler Format Op Code 01 (L, B
1
), 02 (B
2
)
XC 0(4,7) ,8(7) EXCLUSIVE ORs word 1 with word 2 as follows:
Word 1: 0000 0000 0000 0000 0001 0111 1001 00002 = 00 00 17 90 Word 2: 0000 0000 0000 0000 0001 0100 0000 00012 = 00 00 14 01 ResuU: 0000 0000 0000 0000 0000 0011 1001 00012 = 00 00 03 91
The result replaces the former contents of word 1.
Now, execution of the instruction
Machine Format Op Code L B1
°1
B2 °2
07 03 I 7 008 I 7 I 000 Assembler Format Op Code 01 (L,B
1
),02(B
2
)
XC 8(4,7) ,0(7) produces the following result:
Word 1: 0000 0000 0000 0000 0000 0011 1001 00012 = 00 00 03 91
Word 2: 0000 0000 0000 0000 0001 0100 0000 0001 2 = 00 00 14 01 Result: 0000 0000 0000 0000 0001 0111 1001 00002 = 00 00 17 90 Appendix I. Number Representation and Instruction-Use Examples 297