Condition Code: The code remains unchanged.
Program Exceptions: Operation (if the PSW-key-handling feature is not
installed)
Privileged operation
Insert Storage Key ISK [RR]
o 8 12 15
The key in storage associated with the block that is
addressed by the contents of the general register
designated by the R2 field is inserted in the general
register designated by the Rt field.
Bits 8-20 of the register designated by the R2
field designate a block of 2,048 bytes in real main
storage. Bits 0-7 and 21-27 of the register are ig­
nored. Bits 28-31 of the register must be zeros; oth­
erwise, a specification exception is recognized, and
the operation is suppressed.
The address designating the storage block, being a
real address, is not subject to dynamic address trans­
lation. Hence, the reference to the key cannot cause
segment-translation, page-translation, and
translation-specification exceptions to be recognized,
and an addressing exception can be caused only by
an invalid storage-block address (as contrasted to an
invalid address of a table entry). The reference to
the key is not subject to a protection exception.
The execution of the instruction depends on the
mode of operation. When the PSW specifies the
extended-control mode, the complete seven-bit key
is inserted into bit positions 24-30 of the register
designated by the Rt field, with bit 31 set to zero.
When the PSW specifies the basic-control mode, bits 0-4 of the key are placed in bit positions 24-28 of .the register, with bits 29-31 of the register set to
zeros. The contents of bit positions 0-23 of the regis­
ter remain unchanged.
Condition Code: The code remains unchanged.
Program Exceptions:
Privileged operation
Access (addressing for operand access only, oper­
and 2)
Specification
Load Control
LCTL Rl,R3,D2(B2) [RS] B7 I R, I R3 I B2 I D2 I 0 8 12 16 20 31
The set of control registers starting with the control
register designated by the R t field and ending with
the control register designated by the R3 field is
loaded from the locations designated by the second­
operand address.
The storage area from which the contents of the
control registers are obtained starts at the location
designated by the second-operand address and con­
tinues through as many storage words as the number
of control registers specified. The control registers
are loaded in ascending order of their addresses,
starting with the control register designated by the
Rt field and continuing up to and including the con­
trol register designated by the R3 field, with control
register 0 following control register 15. The second
operand remains unchanged.
An attempt is made to fetch the operand from
main storage for each of the designated control reg­
isters, regardless of whether the facility requiring the
presence of the control register is installed. Whenev­
er the storage reference causes an access exception,
the exception is indicated.
The second operand must be designated on a
word boundary; otherwise, a specification exception
is recognized, and the operation is suppressed.
Condition Code: The code remains unchanged.
Program Exceptions:
Privileged operation
Access (fetch, operand 2)
Specification
Programming Note
To ensure that presently written programs run when
new facilities using additional control register posi­
tions are installed, only zeros should be loaded in
unassigned control register positions.
Load PSW LPSW 82 J
o 8 16 20 31
System-Control Instructions 105

The current PSW is replaced by the contents of the
doubleword at the location designated by the _ second-operand address.
If the new PSW specifies the basic-control (BC)
mode, information in bit positions 16-33 of the new PSW is not retained as the PSW is loaded. When the PSW is subsequently stored, these bit positions con­
tain the new interruption code and the instruction­
length code.
A serialization function is performed. CPU oper­
ation is delayed until all previous accesses by this CPU to main storage have been completed, as ob­
served by channels and other CPUs. No subsequent I instructions or their operands are accessed by this CPU until the execution of this instruction is com­
pleted.
The operand must be designated on a doubleword
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. The
operation is suppressed on protection and addressing
exceptions.
The value which is to be loaded by the instruction
is not checked for validity before it is loaded. How­
ever, immediately after loading, a specification ex­
ception is recognized, and a program interruption
occurs, when the value specifies the BC mode and
the BC facility is not installed, or when the value
specifies the EC mode and the contents of bit posi­
tions 0, 2-·4, 16-17, and 24-39 are not all zeros. In
these cases, the operation is completed, and the re­
sulting instruction-length code is zero.
Bits 8-15 of the instruction are ignored.
Resulting Condition Code: The code is set as speci­
fied in the new PSW loaded.
Program Exceptiom: Privileged operation
Access (fetch, operand 2)
Specification
Load Real Address
The real address corresponding to the second·,
operand address is inserted in the general register
designated by the R 1 field. The remaining high-order
bits of the register are set to zeros.
The logical address specified by the X2, B21 and
D2 fields is translated by means ofthe dynamic­
address-translation facility, regardless of whether
106 System/370 Principles of Operation
translation is specified in the PSW, and regardless of
whether the PSW specifies the BC or EC mode. The
translation is performed using the current contents
of control registers 0 and 1, but without the use of
the translation-look aside buffer (TLB). The reSUl­ tant 24-bit real address is inserted in bit positions
8-31 of the general register designated by the Rl
field, and bits 0-7 of the register are set to zeros.
The translated address is not inspected for resolu-
. tion, protection, or validity.
Condition code 0 is set when translation can be
completed, that is, when the entry in each table lies
within the specified table length and its I bit is zero.
When the I bit in the segment-table entry is one,
condition code 1 is set, and the real address of the
segment-table entry is placed in the register desig­
nated by the R 1 field. When the I bit in the page­
table entry is one, condition code 2 is set, and the
real address of the page-tabie entry is placed in the
register designated by the Rl field. When either the
segment-table entry or the page-table entry is out­
side the table, condition code 3 is set, and the regis­
ter designated by the R 1 field contains the real ad­
dress of the entry that would have been referred to if
the length violation did not occur. In all these cases,
the 24-bit address is placed in bit positions 8-31 of
the register, and the leftmost eight bits of the regis­
ter are set to zeros.
An addressing exception is recognized when the
address of the segment-table entry or page-table
entry designates a location outside the available
main storage of the installed system. A translation­
specification exception is recognized when bits 8-12
of control register 0 contain an invalid code, or the
segment-table entry or page-table entry has a format
error. For all these cases, the operation is sup­
pressed.
Resulting Condition Code:
o Translation available
1 Segment-table entry invalid (I bit is one)
2 Page-table entry invalid (I bit is one)
3 Segment-or page-table length violation
Program Exceptions: Operation (if the translation feature is not in­
stalled)
Privileged operation
Access (addressing for table-entry access and
translation specification only, operand 2)