Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 Add Logical
[RR] L_1 E ----l-R-----L.-' I I o 8 12 15
J
D2 _____ o 8 12 16 20 31
The slecond operand is added to the first operand,
and the sum is placed in the first-operand location.
The occurrence of a carry out of the sign position is
recorded in the condition code.
Logical addition is performed by adding all 32
bits of both operands without further change to the
resulting sign bit. The instruction differs from ADD
in the meaning of the condition code and in the ab­
sence of the interruption for overflow.
If a carry out of the sign position occurs, the left­
most bit of the condition code is made one. In the absence of a carry, the bit is made zero. When the
sum is zero, the rightmost bit of the condition code is
made zero. For a nonzero sum, the bit is made one.
Resulting Condition Code:
o Sum is zero, with no carry
1 Sum is not zero, with no carry
2 Sum is zero, with carry
3 Sum is not zero, with carry
Progl'am Exceptions:
Access (fetch, operand 2 of AL only)
AN1)
NR Rl,R2 [RR] 120 System/370 Principles of Operation N R 1 ,D2(X2,B2) [RX] I 54 R, X
2 I B2 I 0 8 12 16 20 31
NI Dl(Bl),h [SI]
[
94 I 12 I B, I 0, I 0 8 16 20 31
NC [SS]
The AND of the first and second operands is placed
in the first-operand location. Operands are treated as unstructured logical
quantities, and the connective AND is applied bit by
bit. A bit position in the result is set to one if the
corresponding bit positions in both operands contain
a one; otherwise, the result bit is set to zero.
For NC, each operand field is processed left to
right. When the operands overlap, the result is ob­
tained as if the operands were processed one byte at
a time and each result byte were stored immediately
after the necessary operand byte is fetched.
Resulting Condition Code:
o Result is zero
1 Result not zero
2 -
3 -
Program Exceptions:
Access (fetch, operand 2, Nand NC; fetch and
store, operand 1, NI and NC)
Programming Note
The instruction AND may be used to set a bit to
zero.
The execution of NI and NC consists in fetching a
first-operand byte from main storage and subse­
quently storing the updated value. These fetch and
store accesses to a particular byte do not necessarily
occur one immediately after the other. Thus, the
instruction AND cannot be safely used to update a
shared location in main storage if the possibility ex­
ists that another CPU or a channel may also be updat­
ing the location. For NI, only one byte is stored.
Branch and Link
BALR RI,R2 [RR] 05 I R, I R2 I 0 8 12 15
BAL RI,D2(X2,B2) [RX]
45
I R, I X
2
I
B2 D2 0 8 12 16 20 31
Information from the current PSW, including the
updated instruction address, is loaded as link infor­
mation in the general register designated by R I. Subse­
quently, the instruction address is replaced by the
branch address.
In the RX format, the second-operand address is
used as the branch a4dress. In the RR format, the
contents of bit positions 8-31 of the general register
designated by R2 are used as the branch address.
However, when the R2 field contains zeros, the op­
eration is performed without branching.
The branch address is computed before the link
information is loaded. The link information, in both
the BC and EC modes, consists of the instruction­
length code, the condition code, the program mask
bits, and the updated instruction address, arranged in
the following format:
Instruction Address I 0 248 31
The instruction-length code is 1 or 2.
Condition Code:
The code remains unchanged.
Program Exceptions:
None When the R2 field in the RR format contains all
zeros, the link information is loaded without branch­
ing. The format and the contents of the link infor­
mation do not depend on whether the PSW specifies
the BC or EC mode.
When BRANCH AND LINK is the subject in­
struction of EXECUTE, the instruction-length code
is 2.
In both the BC and EC modes, the link informa­
tion is in the format of the rightmost 32 bit positions
of the BC-mode PSW. Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
Branch on Condition
BCR MI,R2 [RR] 07 I M, I R2 I 0 8 12 15
BC MI,D2(X2,B2) [RX] I 47 I M, I X 2 I B2 D2 0 8 12 16 20 31
The updated instruction address in the current PSW is replaced by the branch address if the state of the
condition code is as specified by MI; otherwise, nor­
mal instruction sequencing proceeds with the updat­
ed instruction address. I In the RX format the second-operand address is
used as the branch address. In the RR format the
contents of bit positions 8-31 of the general register
specified by R2 are used as the branch address.
However, when the R2 field contains zeros, the oper­
ation is performed without branching.
The MI field is used as a four-bit mask. The four
bits of the mask correspond, left to right, with the
four condition codes (0, 1,2, and 3), as follows:
Instruction Bit Mask Position Value Condition Code 8 8 0 9 4 1 10 2 2
11 3
The branch is successful whenever the condition
code has a corresponding mask bit of one.
When the MI and R2 fields of BCR are 15 and 0, respectively, a serialization function is performed. CPU operation is delayed until all previous storage
accesses by this CPU to main storage have been
completed, as observed by channels and other CPUs. No subsequent instructions or their operands
are· accessed by this CPU until the execution of this
instruction is completed.
Condition Code; The code remains unchanged.
Program Exceptions:
None When a branch is to be made on more than one con­
dition code, the pertinent condition codes are speci­
fied in the mask as the sum of their mask position
values. A mask of 12, for example, specifies that a
General Instructions 121
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