Programming Note
The name "branch on index high" indicates that one
of the major purposes of this instruction is the incre­
menting and testing of an index value. The incre­
ment may be algebraic and of any magnitude.
Branch on Index Low or Equal
BXLE [RS]
o 8 12 16 20 31
An increment is added to the first operand, and the
sum is compared algebraically with a comparand.
Subsequently, the sum is placed in the first-operand
location, regardless of whether the branch is taken.
The second-operand address is used as the branch
address.
When the sum is low or equal, the instruction
address in the current PSW is replaced by the branch
address. When the sum is high, normal instruction
sequencing proceeds with the updated instruction
address.
The first operand and the increment are in the
registers specified by Rl and R3. The comparand
register address is odd and is either one larger than
R3 or equal to R3. The branch address is computed
before the addition and comparison.
This instruction is similar to BRANCH ON IN­
DEX HIGH, except that the branch is successful
when the sum is low or equal compared to the com­
parand.
Condition Code:
The code remains unchanged.
Program Exceptions:
None
Compare
CR Rl,R2 [RR]
19 I R, I R2 I 0 8 12 15
C Rl,D2(X2,B2) [RX]
59 I R, I X
2 I B2 I D2 I 0 8 12 16 20 31
The first operand is compared with the second oper­
and, and the result determines the setting of the
condition code.
Comparison is algebraic., treating both compa­
rands as 32-bit signed integers. Operands in regis­
ters or storage are not changed.
Resulting Condition Code:
o Operands are equal
1 First operand is low
2 First operand is high
3 -
Program Excepfiom:
Access (fetch, operand 2 of Conly)
Compare and Swap CS [RS]
BA
o 8 12 16 20 31
The first and second operands are compared. If they
are equal, the third operand is stored in the second­
operand location. If they are unequal, the second
operand is loaded into the first-operand location.
The first and third operands are 32 bits in length,
with each operand occupying a general register. The
second operand is a word in main storage.
The result of the 32-bit comparison, either equal
or unequal, is used to set the condition code. When
the result of the comparison is unequal, no attempt
to store occurs, and no change-bit and store­
protection actions are taken.
When an equal comparison occurs, no access by
another CPU is permitted at the second-operand
location between the moment that the second oper­
and is fetched for comparison and the moment that
the third operand is stored at the second-operand
location.
A serialization function is performed before the
operand is fetched, and, if condition code 0 is set,
after the result is stored. CPU operation is delayed
until all previous accesses by this CPU to main stor­
age have been completed, as observed by channels
and other CPU s, and then the second operand is
fetched. No subsequent instructions or their oper­
ands are accessed by this CPU until the execution
of this instruction is completed, including placing the
result value, if any, in main storage, as observed by
channels and other CPUs.
The second operand must be designated on a '<';':1 word boundary; otherwise, a specification is recognized, and the operation is suppressed ....... General Instructions 123

Resulting Condition Code:
o First and second operands equal, second oper­ and replaced by third operand
1 First and second operands unequal, first oper­
and replaced by second operand
2 -
3 - Program Exceptions:
Operation (if the conditional-swapping feature is
not installed) Specification Access (fetch and store, operand 2)
Programming Notes
The instruction COMPARE AND SWAP ean be
used by programs sharing common storage areas in
either a multiprogramming or multiprocessing envi­
ronment. The following are two examples:
By performing the following procedure, a pro­
gram can modify the contents of a storage location
even though the possibility exists that the program
may be interrupted by another program that will
update the location or even though the possibility
exists that another CPU may simultaneously update
the location. First, the entire word containing the
byte or bytes to be updated is loaded into a general
register. Next, the updated value is computed and
placed in another general register. Then the instruc­
tion AND SWAP is executed with the
Rl field designating the register that contains the
original value and the R3 field designating the regis­
ter that contains the updated value. If condition code
o is set, the update has been successful. If condition
code 1 is set, the storage location no longer contains
the original value, the update has not been success­
ful, and the general register designated by the Rl
field of the COMPARE AND SWAP instruction
contains the new current value of the storage loca­
tion. When condition code 1 is set, the program can
repeat the procedure using the new current value. COMPARE AND SWAP may be used for con­
trolled sharing of a common storage area in a man­
ner similar to that described in the programming
note unde:r TEST AND SET, but it provides the
added capability of leaving a message when the com­
mon area is in use. To accomplish this, a word in
storage may be used as a control word, with a zero
value in the word indicating that the common area is
not in use, a negative value indicating that the area is
in use, and a nonzero positive value indicating that
the common area is in use and that the value is the
address of the most recent message added to the list.
Thus, any number of programs desiring to seize the
124 System/370 Principles of Operation area may use COMPARE AND SWAP to update
the control word to indicate that the area is in use or
to add messages to the list. The single program
which has seized the area may also safely use COM­ P ARE AND SW AP to remove messages from the
list.
It should be noted that COMPARE AND SWAP does not interlock against storage accesses by chan­
nels. Therefore, the instruction should not be used to
update a word, all or part of which is in an 110 input
area, since the input data may be lost.
Compare Double and Swap
CDS [RS]
BB
o 8 12 16 20 31
The first and second operands are compared. If they
are equal, the third operand is stored in the second­
operand location. If they are unequal, the second
operand is loaded into the first-operand location.
The first and third operands are 64 bits in length,
with each operand occupying an even-odd pair of
general registers. The second operand is a double­
word in main storage.
The result of the 64-bit comparison, either equal
or unequal, is used to set the condition code. When
the result of the comparison is unequal, no attempt
to store occurs, and no change-bit and store-
protection actions are taken. .
When an equal comparison occurs, no access by
another CPU is permitted at the second-operand
location between the moment that the second oper­
and is fetched for comparison and the moment that
the third operand is stored at the second-operand
location.
A serialization function is performed before the
operand is fetched, and, if condition code 0 is set,
after the result is stored. CPU operation is delayed
until all previous accesses by this CPU to main stor­
age have been completed, as observed by channels
and other CPUs, and then the second operand is
fetched. No subsequent instructions or their oper­
ands are accessed by this CPU until the instruction
is completed, including placing the result value, if
any, in main storage, as observed by channels and
other CPUs. The R 1 and R3 fields must each designate an even
register, and the second operand must be designated <,?n a double word boundary; otherwise, a specific a­ tiOiiexceptiolfis recogniied;--arid"lhe operation is
suppressed.