The storage area where the contents of the gener­
al registers are placed starts at the location designat­
ed by the second-operand address and continues
through as many locations as needed. The general
registers are stored in the ascending order of their
addresses, starting with the register specified by Rl
and continuing up to and including the register speci­
fied by R3, with register 0 following register 15.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (store, operand 2)
Subtract
SR [RR]
o 8 12 15
S [RX]
58
o 8 12 16 20 31
The second operand is subtracted from the first oper­
and, and the difference is placed in the first-
operand location.
Subtraction is considered to be performed by
adding the one's complement of the second operand
and a low-order one to the first operand. All 32 bits
of both operands participate, as in ADD. If the carry
out of the sign-bit position and the carry out of the
high-order numeric bit position agree, the difference
is if they disagree, an overflow occurs.
The overflow causes a program interruption when
the fixed-point overflow mask bit is one.
Resulting Condition Code:
o Difference is zero
1 Difference is less than zero
2 Difference is greater than zero 3 Overflow
Program Exceptions:
Access (fetch, operand 2 of S only)
Fixed-Point Overflow
Programming Note
The use of the one's complement and the low-order
one instead of the two's complement of the second
operand is necessary for proper recognition of over­
flow when subtracting the maximum negative num­
ber.
When, in the RR format, the Rl and R2 fields
designate the same register, subtracting is equivalent
to clearing the register.
Subtracting a maximum negative number from
another maximum negative number gives a zero re­
sult and no overflow.
Subtract Hal/word
SH [RX]
48
l
o 8 12 16 20 31
The second operand is subtracted from the first oper­
and, and the difference is placed in the first-operand
location. The second operand is two bytes in length
and is considered to be a 16-bit signed integer.
The second operand is expanded to 32 bits before
the subtraction by propagating the sign-bit value
through the 16 high-order bit positions.
Subtraction is considered to be performed by
adding the one's complement of the expanded sec­
ond operand and a low-order one to the first oper­
and. All 32 bits of both operands participate, as in
ADD. If the carry out of the sign-bit position and
the carry out of the high-order numeric bit position
agree, the difference is if they disagree,
an overflow occurs. The overflow causes a program
interruption when the fixed-point overflow mask bit
is one.
Resulting Condition Code:
o Difference is zero
1 Difference is less than zero
2 Difference is greater than zero
3 Overflow
Program Exceptions:
Access (fetch, operand 2)
Fixed-Point Overflow
Subtract Logical
SLR [RR]
1F
o 8 12 15
SL
o 8 12 16 20 31
General Instructions 143

The second operand is subtracted from the first oper­
and, and the difference is placed in the first-
operand location. The occurrence of a carry out of
the sign position is recorded in the condition code.
Logical subtraction is considered to be performed
by adding the one's complement of the second oper­
and and a low-order one to the first operand. All 32
bits of both operands participate, without further
change to the resulting sign bit. The instruction dif­
fers from SUBTRACT in the meaning of the condi­
tion code and in the absence of the interruption for
overflow.
If a carry out of the sign position occurs, the left­
most bit of the condition code is made one. In the
absence of a carry, the bit is made zero. When the
sum is zero, the rightmost bit of the condition code
is made zero. For a nonzero sum, the bit is made
one. Resulting Condition Code:
o -
1 Difference is not zero, with no carry
2 Difference is zero, with carry
3 Difference is not zero, with carry
Program Exceptions:
Access (fetch, operand 2 of SL only)
Programming Note
The use of the one's complement and the low-order
one instead of the two's complement of the second
operand results in the recognition of carry when
subtracting zero or the maximum negative number.
A zero difference cannot be obtained without a car­
ry out of the sign position. Superl'isor Call SVC [RR]
o 8 15
The instruction causes a supervisor-call interruption,
with the I field of the instruction providing the inter­
ruption Icode. The contents of bit positions 8-15 of the instruc­
tion, with eight high-order zeros appended, are
placed in the supervisor-call interruption code that is
stored in the course of the interruption. The old PSW is stored at location 32, and a new PSW is ob­
tained from location 96. The instruction is valid in
both the problem and supervisor states.
144 System/370 Principles of Operation Condition Code:
The code remains unchanged in the old PSW. Program Exceptions:
None
Test and Set TS [S] The leftmost bit (bit position 0) of the byte located
at the second-operand address is used to set the con­ I dition code, and then the entire addressed byte is set
to all ones. Bits 8-15 of the instruction are ignored.
The byte in storage is set to all ones as it is
fetched for the testing of bit position O. No access by
another CPU is permitted to this location between
the moment of fetching and the moment of storing
all ones.
A serialization function is performed before the
byte is fetched and again after the storing of all
ones. CPU operation is delayed until all previous
accesses by this CPU to main storage have been
completed, as observed by channels and other CPUs, and then the byte is fetched. No subsequent
instructions or their operands are accessed by this CPU until the all-ones value has been placed in main
storage, as observed by channels and other CPUs. Resulting Condition Code:
o Leftmost bit of byte specified is zero
1 Leftmost bit of byte specified is one
2 -
3 -
Program Exceptions:
Access (fetch and store, operand 2)
Programming Note TEST AND SET can be used for controlled sharing
of a common storage area by more than one pro­
gram. To accomplish this, bit position 0 of a byte
must be designated as the control bit. The desired
interlock can be achieved by establishing a program
convention in which a zero in the bit position indi­
cates that the common area is available but a one
means that the area is being used. Each using pro­
gram then must examine this byte by means of TEST AND SET before making access to the com­
mon area. If the test sets condition code 0, the area
is available for use; if it sets condition code 1, the