tions with channel end. The control-unit-end and
device-end conditions can be accompanied by error
indications from the device.
Facilities are provided for the program to initiate
execution of a chain of I/O operations with a single
START I/O or START I/O FAST RELEASE.
When the chaining flags in the current CCW specify
command chaining and no unusual conditions have
been detected in the operation, the receipt of the
device end signal causes the channel to fetch a new
CCW and to initiate a new command at the device.
A chained command is initiated by means of the
same sequence of signals over the I/O interface as
the first command specified by ST ART I/O or
ST ART I/O FAST RELEASE. The ending signals
occurring at the concluding of an operation caused
by a CCW specifying command chaining are not
made available to the program when another opera­
tion is initiated by the command chaining; the chan­
nel continues execution of the channel program. If,
however, an unusual condition has been detected,
the ending signals cause suppression of command
chaining and a termination of the channel program.
Conditions that initiate I/O interruptions are
asynchronous to activity in the CPU, and more than
one condition can occur at the same time. The chan­
nel and the CPU establish priority among the condi­
tions so that only one interruption request is pro­
cessed at a time. The conditions are preserved in the I/O devices or subchannels until accepted by the CPU. Execution of an I/O operation or chain of opera­
tions thus involves up to four levels of participation:
1. Except for the effects caused by the integration
of CPU and channel equipment, the CPU is
busy for the duration of execution of START I/O or START I/O FAST RELEASE, which
lasts at most until the addressed I/O device
responds to the first command.
2. The subchannel is busy with the execution
from the initiation of the operation at the I/O device until the channel-end condition for the
last operation of the command chain is accept­
ed by the CPU. 3. The control unit may remain busy after the
subchannel has been released and may gener­
ate the control-unit-end condition when it be­
comes free.
4. The I/O device is busy from the initiation of
the first operation until the device-end condi­
tion associated with the operation is accepted
or cleared by the CPU. A pending device-end condition causes the associ­
ated device to appear busy, but normally does not
affect the state of any other part of the system. A
pending control-unit-end condition normally blocks
communications through the control unit to any de­
vice attached to it, and a pending channel-end condi­
tion normally blocks all communications through the
sub channel.
Compatibility of Operation
The organization of the I/O system provides for a
uniform method of controlling I/O operations. The
capability of a channel, however, depends on its use
and on the CPU model to which it is attached.
Channels are provided with different data-transfer
capabilities, and an I/O device designed to transfer
data only at a specific rate (a magnetic tape unit or a
disk storage, for example) can operate only on a
channel that can accommodate at least this data rate.
The data rate a channel can accommodate de-
pends also on the way the I/O operation is programmed.
The channel can sustain its highest data rate
when no data chaining is specified. Data chaining
reduces the maximum allowable rate, and the extent
of the reduction depends on the frequency at which
new CCWs are fetched and on the address resolu-
tion of the first byte in each new main-storage area.
Furthermore, since in most instances the channel
may share main storage with the CPU and other
channels, activity in the rest of the system affects the
accessibility of main storage and, hence, the instan­
taneous load the channel can sustain.
In view of the dependence of channel capacity on
programming and on activity in the rest of the sys­
tem, an evaluation of the ability of elements in a
specific I/O configuration to function concurrently
must be based on a consideration of both the data
rate and the way the I/O operations are programmed.
Two systems employing identical complements of I/O devices may be able to execute certain programs
in common, but it is possible that other programs
requiring, for example, data chaining, may not run
on one of the systems because of the increased load
caused by the data chaining.
Control of Input/ Output Devices I The CPU controls I/O operations by means of eight I/O instructions: START I/O, START I/O FAST RELEASE,TESTI/O,CLEARI/O,HALTI/O, I HALT DEVICE, TEST CHANNEL, and STORE CHANNELID.
The instruction TEST CHANNEL and STORE CHANNEL ID address a channel; they do not ad­ I dress an I/O device. The other six I/O instructions
address a channel and a device on that channel.
Input/Output Operations 191
Input / Output Device Addressing
An I/O device and the associated access path are
designated by an I/O address. The I/O address is a
16-bit binary number and consists of two parts: a
channel address in the eight high-order bit positions
and a device address in the eight low-order bit posi­
tions.
The channel-address field provides for identifying
up to 256 channels. Channel 0 is a byte-multiplexer channel; channels numbered 1-255 may be either
multiplexer or selector channels.
The number and type of channels available, as
well as their address assignment, depend on the sys­
tem model and the particular installation.
The device address identifies the particu1ar I/O device and control unit on the designated channel.
The address identifies, for example, a particular
magnetic tape drive, disk-access mechanism, or
transmission line. Any number in the range 0-255 can be used as a device address, providing facilities
for addressing up to 256 devices per channel. An
exception is some byte-multiplexer channels that provide fewer than the maximum configuration of
subchannels and hence eliminate the corresponding
unassignable device addresses.
Devices that do not share a control unit with oth­
er devices may be assigned any device address in the
range 0-255, provided the address is not recognized
by any other control unit. Logically, such devices are
not distinguishable from their control unit, and both
are identified by the same address.
Devices sharing a control unit (for example, mag­
netic tape drives or disk-access mechanisms) are
assigned addresses within sets of contiguous num­
bers. The size of such a set is equal to the maximum
number of devices that can share the control unit, or
16, whichever is smaller. Furthermore, such a set
starts with an address in which the number of low­
order zeros is at least equal to the number of bit
positions required for specifying the set size. The
high-order bit positions of an address within such a set identify the control unit, and the low-order bit
positions designate the device on the control unit.
Control units designed to accommodate more than
16 devices may be assigned nonsequential sets of ad­
dresses, each set consisting of 16, or the number re­
quired to bring the total number of assigned addresses equal to the maximum number of devices attachable
to the control unit, whichever is smaller. The address­ ing facilities are added in increments of a set so that
the number of device addresses assigned to a control
unit does not exceed the number of devices attached
by more than 15. 192 System/370 Principles of Operation
The control unit does not respond to any address
outside its assigned set or sets. For example, if a
control unit is designed to control devices having
only bits 0000-1001 in the low-order positions of
the device address, it does not recognize addresses
containing 1010-1111 in these bit positions. On the
other hand, a control unit responds to all addresses
in the assigned set, regardless of whether the device
associated with the address is installed. For example,
the IBM 3830 Storage Control Model 2, with four
disk units installed, responds to all of the 16 address­
es within the set assigned to it. If no control unit
responds to an address, the I/O device appears not
operational. If a control unit responds to an address
for which no device is installed, the absent device
appears in the not-ready state.
Input/ output devices accessible through more
than one channel have a distinct address for each
path of communications. This address identifies the
channel and the control unit. For sets of devices
connected to two or more control units, the portion
of the address identifying the device on the control
unit is fixed, and does not depend on the path of
communications.
Except for the rules described, the assignment of
channel and device addresses is arbitrary. The as­
signment is made at the time of installation, and the
addresses normally remain fixed thereafter.
States of the Input/Output System
The state of the I/O system identified by an I/O address depends on the collective state of the chan­
nel, subchannel, and I/O device. Each of these com­
ponents of the I/O system can have up to four
states, as far as the response to an I/O instruction is
concerned. These states are listed in the following
table. The name of the state is followed by its abbre­
viation and a brief definition.
A portion of the 110 system that is available,
interruption-pending, or working is called "operational." A portion of the I/O system that is
interruption-pending, working, or not-operational is
called "not available."
In the case of a multiplexer channel, the channel
and subchannel are easily distinguishable and, if the
channel is operational, any combination of channel
and subchannel states is possible. Since the selector
channel can have only one subchannel, the channel
and subchannel are functionally coupled, and certain
states of the channel are related to those of the sub­
channel. In particular, the working state can occur
only concurrently in both the channel and subchan­
nel and, whenever an interruption condition is pend-
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