identifying the PER condition is stored in its regular
format in locations150-155. Program-event recording applies to all instruc
tions, including the special-purpose instructions,
such as those provided for emulation. The latter
class of instructions indicates all events that have
occurred and may additionally indicate events that
did not occur and were not called for in the instruc
tion, provided monitoring was enabled for the type
of event by thePER mask in the PSW and the PER event masks, bits 0-3 in control register 9. In such
cases, the contents of the remaining positions in
control registers 9,10, and 11 may be ignored. Thus,
for example, a special-purpose instruction may cause
general-register alteration to be indicated even
though no general registers are altered, and even. though bits 16-31 of control register 9 are all zeros.
Identification of Cause
The cause of the interruption is identified by setting
bit 8 of the interruption code to one and by the in
formation placed in locations150-155 of main stor
age. The interruption code on a program-event inter
ruption may indicate concurrently a program event
and another program-interruption condition. The
format of the information stored in locations150- 155 is as follows:
Locations150-151: I P.C. 1000000000000 1 o 4 15
Locations 152-155:1000000001 o 8
PER Address
31
The event causing a program-event interruption is
identified by a one in bit positions0-3 of location 150, the PER code, with the rest of the bits in the
code set to zeros. The bit position in thePER code
for a particular event is the same as the bit position
forthat event in the PER event-mask field. When a PER interruption occurs and more than one desig
nated program event has been recognized, all recog
nized program events are concurrently indicated in
thePER code.
ThePER address at locations 153-155 identifies
the location of the instruction causing the event.
When the instruction is executed by means of EX
ECUTE, the address of the location containing the
EXECUTE instruction is placed in the PER-address
field. In either case, the address of the instruction to
be executed next is placed in thePSW. Zeros are
stored in bit positions 4-7 of location150 and at
locations 151 and 152.
Priority of Indication
When the execution of an interruptible instruction is
due to be interrupted by anI/O, external, or
machine-check-recovery condition, the program
event interruption occurs first, and theI/O, external,
or machine-check interruption is subsequently sub
ject to the control of mask bits in the newPSW. Similarly, when the CPU is placed in the stopped
state during the execution of an interruptible instruc
tion, an interruption for a pendingPER condition
occurs before the stopped state is entered. When a
dynamic-address-translation (DAT) exception is
encountered, the pendingPER condition is indicated
concurrently with the DAT condition. Normally a
program event does not cause premature interrup
tion of the interruptible instruction unless some oth
er event is due to cause an asynchronous interrup
tion. However, depending on the model, in certain
situations, aPER condition may cause the execution
of an interruptible instruction to be interrupted with
out an associated asynchronous condition or pro
gram exception.
In the case of an instruction-fetching event onSUPERVISOR CALL, the PER interruption occurs
immediately after the supervisor-call interruption.
Programming Notes
In the following cases an instruction can both cause
aPER interruption and change the value of bits con
trolling the occurrence of aPER interruption for
that particular event. In these cases the original val
ues of the control bits determine whether aPER interruption occurs.
t. The instructionsLOAD PSW, SET SYSTEM MASK, STORE THEN AND SYSTEM MASK, and SUPERVISOR CALL can cause
an instruction-fetching event and disable theCPU for PER interruptions. Additionally, STORE THEN AND SYSTEM MASK can
cause storage alteration to be indicated. In all
these cases, the old programPSW associated
with the program-event interruption may indi
cate that theCPU was disabled for the inter
ruption.
2. The instructionLOAD CONTROL may cause
an instruction-fetching event and change the
value of thePER event masks in control regis
ter 9 or the addresses in control registers10 and 11 controlling indication of the instruction
fetching event.
System Control 41
format in locations
tions, including the special-purpose instructions,
such as those provided for emulation. The latter
class of instructions indicates all events that have
occurred and may additionally indicate events that
did not occur and were not called for in the instruc
tion, provided monitoring was enabled for the type
of event by the
cases, the contents of the remaining positions in
control registers 9,
for example, a special-purpose instruction may cause
general-register alteration to be indicated even
though no general registers are altered, and even
Identification of Cause
The cause of the interruption is identified by setting
bit 8 of the interruption code to one and by the in
formation placed in locations
age. The interruption code on a program-event inter
ruption may indicate concurrently a program event
and another program-interruption condition. The
format of the information stored in locations
Locations
Locations 152-155:
PER Address
31
The event causing a program-event interruption is
identified by a one in bit positions
code set to zeros. The bit position in the
for a particular event is the same as the bit position
for
nated program event has been recognized, all recog
nized program events are concurrently indicated in
the
The
the location of the instruction causing the event.
When the instruction is executed by means of EX
ECUTE, the address of the location containing the
EXECUTE instruction is placed in the PER-address
field. In either case, the address of the instruction to
be executed next is placed in the
stored in bit positions 4-7 of location
locations 151 and 152.
Priority of Indication
When the execution of an interruptible instruction is
due to be interrupted by an
machine-check-recovery condition, the program
event interruption occurs first, and the
or machine-check interruption is subsequently sub
ject to the control of mask bits in the new
state during the execution of an interruptible instruc
tion, an interruption for a pending
occurs before the stopped state is entered. When a
dynamic-address-translation (DAT) exception is
encountered, the pending
concurrently with the DAT condition. Normally a
program event does not cause premature interrup
tion of the interruptible instruction unless some oth
er event is due to cause an asynchronous interrup
tion. However, depending on the model, in certain
situations, a
of an interruptible instruction to be interrupted with
out an associated asynchronous condition or pro
gram exception.
In the case of an instruction-fetching event on
immediately after the supervisor-call interruption.
Programming Notes
In the following cases an instruction can both cause
a
trolling the occurrence of a
that particular event. In these cases the original val
ues of the control bits determine whether a
t. The instructions
an instruction-fetching event and disable the
cause storage alteration to be indicated. In all
these cases, the old program
with the program-event interruption may indi
cate that the
ruption.
2. The instruction
an instruction-fetching event and change the
value of the
ter 9 or the addresses in control registers
fetching event.
System Control 41