identifying the PER condition is stored in its regular
format in locations 150-155. Program-event recording applies to all instruc­
tions, including the special-purpose instructions,
such as those provided for emulation. The latter
class of instructions indicates all events that have
occurred and may additionally indicate events that
did not occur and were not called for in the instruc­
tion, provided monitoring was enabled for the type
of event by the PER mask in the PSW and the PER event masks, bits 0-3 in control register 9. In such
cases, the contents of the remaining positions in
control registers 9, 10, and 11 may be ignored. Thus,
for example, a special-purpose instruction may cause
general-register alteration to be indicated even
though no general registers are altered, and even . though bits 16-31 of control register 9 are all zeros.
Identification of Cause
The cause of the interruption is identified by setting
bit 8 of the interruption code to one and by the in­
formation placed in locations 150-155 of main stor­
age. The interruption code on a program-event inter­
ruption may indicate concurrently a program event
and another program-interruption condition. The
format of the information stored in locations 150- 155 is as follows:
Locations 150-151: I P.C. 1000000000000 1 o 4 15
Locations 152-155: 1000000001 o 8
PER Address
31
The event causing a program-event interruption is
identified by a one in bit positions 0-3 of location 150, the PER code, with the rest of the bits in the
code set to zeros. The bit position in the PER code
for a particular event is the same as the bit position
for that event in the PER event-mask field. When a PER interruption occurs and more than one desig­
nated program event has been recognized, all recog­
nized program events are concurrently indicated in
the PER code.
The PER address at locations 153-155 identifies
the location of the instruction causing the event.
When the instruction is executed by means of EX­
ECUTE, the address of the location containing the
EXECUTE instruction is placed in the PER-address
field. In either case, the address of the instruction to
be executed next is placed in the PSW. Zeros are
stored in bit positions 4-7 of location 150 and at
locations 151 and 152.
Priority of Indication
When the execution of an interruptible instruction is
due to be interrupted by an I/O, external, or
machine-check-recovery condition, the program­
event interruption occurs first, and the I/O, external,
or machine-check interruption is subsequently sub­
ject to the control of mask bits in the new PSW. Similarly, when the CPU is placed in the stopped
state during the execution of an interruptible instruc­
tion, an interruption for a pending PER condition
occurs before the stopped state is entered. When a
dynamic-address-translation (DAT) exception is
encountered, the pending PER condition is indicated
concurrently with the DAT condition. Normally a
program event does not cause premature interrup­
tion of the interruptible instruction unless some oth­
er event is due to cause an asynchronous interrup­
tion. However, depending on the model, in certain
situations, a PER condition may cause the execution
of an interruptible instruction to be interrupted with­
out an associated asynchronous condition or pro­
gram exception.
In the case of an instruction-fetching event on SUPERVISOR CALL, the PER interruption occurs
immediately after the supervisor-call interruption.
Programming Notes
In the following cases an instruction can both cause
a PER interruption and change the value of bits con­
trolling the occurrence of a PER interruption for
that particular event. In these cases the original val­
ues of the control bits determine whether a PER interruption occurs.
t. The instructions LOAD PSW, SET SYSTEM MASK, STORE THEN AND SYSTEM MASK, and SUPERVISOR CALL can cause
an instruction-fetching event and disable the CPU for PER interruptions. Additionally, STORE THEN AND SYSTEM MASK can
cause storage alteration to be indicated. In all
these cases, the old program PSW associated
with the program-event interruption may indi­
cate that the CPU was disabled for the inter­
ruption.
2. The instruction LOAD CONTROL may cause
an instruction-fetching event and change the
value of the PER event masks in control regis­
ter 9 or the addresses in control registers 10 and 11 controlling indication of the instruction­
fetching event.
System Control 41
No instructions can both change the values of
general-register alteration masks and cause a
general-register alteration event to be recognized.
When a PER interruption occurs during the execu­
tion of an interruptible instruction, the ILC indi­
cates length of that instruction or EXECUTE, as
appropriate. When a PER interruption occurs as a
result of LOAD PSW or SUPERVISOR CALL, the
ILC indicates the length of these instructions or EX­
ECUTE, as appropriate, unless a concurrent specifi­
cation exception on LOAD PSW calls for an ILC of O. When a PER interruption is caused by branching,
the PER address identifies the branch instruction (or
EXECUTE, as appropriate), whereas the old PSW points to the next instruction to be executed. When
the interruption occurs during the execution of an
interruptible instruction, the PER address and the
instruction address in the old PSW are the same.
Storage Area Designation
Two of the program events--instruction fetching and
storage alteration--involve the designation of an area
in main storage. The storage area monitored for the
references starts at the location designated by the
starting address in control register 10 and extends up
to and including the location designated by the end­
ing address in control register 11. The area extends
to the right of the starting address.
When dynamic address translation is specified,
the storage area is designated by logical when dynamic address translation is suppressed,
control registers 10 and 11 contain real addresses.
The s,et of locations designated for monitoring
purposes wraps around at location 16,777,215; that
is, location 0 is considered to follow location
16,777,215. When the starting address is smaller
than the ending address, the area is contiguous.
When the starting address is larger than the ending
address, the set of locations designated for monitor­
ing purposes includes the area from the starting ad­
dress to the largest address in the system and the
area from location 0 to, and including, the ending
address. When the starting address is equal to the
ending address, only the location designated by that
address is monitored.
The monitoring of main-storage alteration and
instruction fetching is performed by carrying out the
address on all 24 bits of the addresses. Events
Successful Branching
Execution of a successful branch operation causes a
program-event interruption if bit 0 of the PER- 42 System/370 Principles of Operation
event-mask field is one and the PER mask in the PSW is one.
A successful branch occurs whenever one of the
following instructions causes control to be passed to
the instruction designated by the branch address:
BRANCH ON CONDITION BRANCH AND LINK
BRANCH ON COUNT BRANCH ON INDEX HIGH
BRANCH ON INDEX LOW OR EQUAL
The branch event is also indicated by special-
purpose instructions, such as those provided for em­
ulation, when the special-purpose instruction causes
a branch. That is, the location of the next instruc­
tion executed by the CPU after leaving emulation
mode does not immediately follow the location of
the instruction which caused the CPU to enter the
mode.
The event is identified by setting bit 0 of the PER code to one.
Instruction Fetching
Fetching the first byte of an instruction from the
main-storage area designated by the contents of
control registers 10 and 11 causes a program-event
interruption if bit 1 of the PER-event-mask field is
one and the PER mask in the PSW is one.
A program event is recognized whenever the CPU executes an instruction whose initial byte is located
within the monitored area. When the instruction is
executed by means of EXECUTE, a program event
is recognized when the first byte of the EXECUTE
instruction or the subject instruction or both is locat­
ed in the monitored area.
The event is identified by setting bit 1 of the PER code to one.
Storage Alteration
Storing of data by the CPU in the main-storage area
designated by the contents of control registers 10 and 11 causes a program-event interruption if bit 2
of the PER-event-mask field is one and the PER mask in the PSW is one.
The contents of main storage are considered to
have been altered whenever the CPU executes an
instruction that causes the whole operand or part of
it to be stored within the monitored area of main
storage. Alteration is considered to take place when­
ever storing is considered to take place for purposes
of indicating protection exceptions. (See "Recognition of Access Exceptions" in the chapter
"Interruptions. ") An arithmetic or movement opera­
tion is considered to fetch the operand, perform the
indicated operation, if any, and then store the result. Such storing into main storage constitutes alteration
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