Can Copy of Table Entry Be State of Table Entry in TLB ?
Active Attached Valid Yes
Active Attached Invalid Yes
1
Active Unattached Valid Yes
1
Active Unattached Invalid Yes
1 Inactive Attached Valid * Inactive Attached Invalid No Inactive Unattached Valid No Inactive Unattached Invalid No Explanation: Can Table Entry
Be Fetched for Translation ?
Yes
Yes
No
No
*
Yes
No
No
Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
Can Table Entry Can TLB Copy Be
Be Used for Fetched for Implicit Translation? Translation? Yes Yes
No Yes
No No
No No
No No
No No
No No
1 The TLB may contain a copy of a previously attached and valid entry.
* This state cannot exist. An attached and valid table entry is active. Use of Translation Tables
3. When any change is made to an invalid entry in
such a way as to cause intermediate valid val­
ues to appear in the entry, each CPU to which
the entry is attached must issue PURGE TLB
after the change occurs and prior to the use of
the entry for implicit address translation by
that CPU. Note that when an invalid page-table entry is
made valid introducing intermediate valid
values, the TLB need not be purged in a CPU in
which the entry previously was inactive. Similarly,
when an invalid segment-table entry is made valid
without introducing intermediate valid values, the
TLB need not be purged in a CPU in which the
segment-table entry and all page-table entries
attached by it previously were inactive.
Execution of the PURGE TLB instruction may
have an adverse effect on the performance of some
models. Use of this instruction should, therefore, be
minimized in conformity with the above rules.
Reference and Change Recording
Reference recording provides information for use in
selecting storage blocks for page replacement.
Change recording provides information as to which
pages have to be saved when they are replaced by
new pages. Both reference and change recording are
associated with the dynamic-address-translation
facility.
When the dynamic-address-translation facility is
installed, the key in storage is extended with two
additional bits. Bit 5, the reference bit, normally is
set to one each time a location in the corresponding
storage block is referred to either for storing or
fetching of information. Bit 6, the change bit, is set
to one each time information is stored in the corre­
sponding storage block. The recording of references
and changes is not contingent on whether the CPU is in the extended-control or basic-control mode or
whether address translation is specified.
Reference and change recording takes place for
any main-storage access and applies to accesses
made by a CPU, as well as to those due to II 0 ations. Hence, references to a main-storage location
associated with interruptions and 110 instructions,
such as occur to the CAW, CSW, or PSW locations,
are included. A translation-table lookup in the pro­
cess of address translation is considered a reference, provided the table in main storage has actually been
referred to. It is unpredictable whether updating of
the interval timer causes change and reference bits
for location 80 to be turned on. References to the
operand locations of SET STORAGE KEY, IN­ SERT STORAGE KEY, and RESET REFERENCE
BIT do not cause reference or change to be record­
ed.
The change bit is not turned on for an attempt to
store if the storage reference is not permitted, re­
gardless of whether the CPU instruction responsible
for the reference is suppressed or terminated. In
particular, a CPU reference causing a protection,
addressing, segment-translation, or page-translation
exception, or an 110 reference to an invalid or pro­
tected location does not cause the change bit to be
turned on.
The record of references provided by the refer­
ence bit is substantially accurate. The reference bit
may be turned on by fetching data or instructions
that are neither designated nor used by the program,
and, under certain conditions, a reference may be
made without the reference bit being turned on.
Under certain unusual conditions, a reference bit
that is on may be turned off by other than explicit
program action.
Reference and change recording operates on
2,048-byte blocks regardless of the page size in-
Dynamic Address Translation 67

yoked. With a 4,096-byte page size, two keys are
associated with a page.
Programming Note
The accuracy of reference recording is such as to
allow for effective operation of paging algorithms.
The: reference bit cannot be used to establish the
usage of pages containing translation tables since,
after the initial reference, the tables may be used by
means of references to the translation-Iookaside
buffer, without any fetching of the table entries from
main storage. Address- Translation Exceptions
When the dynamic-address-translation facility is installc!d, three additional program-exception condi­
tions (llre introduced: segment-translation exception, page-translation exception, and translation­
specification exception. The CPU cannot be disabled
for translation exceptions. Tht! presence .of the dynamic-address-translation
facility also introduces new conditions that are rec­ ognized as addressing exceptions. When address
translation is invoked, an addressing exception is
recognized when an attempt is made to use a
segment-table entry or a page-table entry that is
designated at a location outside the available main
storage of the installed system. The unit of operation
is suppressed.
The handling of all exceptions associated with
dynamic address translation is summarized in the
table "Handling of Access Exceptions" in the chap­
ter "Interruptions." Summary of Dynamic Address
Translation Formats
The first table summarizes the possible combina­
tions of the page-address and byte-index fields in the
formation of a real storage address.
The eight-bit length field in control register 1
provides for a maximum length code of 255 and
permits designating a segment table of 16,384 bytes,
or 4,096 entries, which is more than can be referred
to for translation purposes by the logical address.
With 1M-byte segments, only 16 segments can be
addressed, requiring a segment table of 64 bytes. A
table of 64 bytes is specified by a length code of ° and is the smallest table that can be specified. With
64K-byte segments, up to 256 segments can be ad­
dressed, requiring at the most a segment table of
1,024 bytes and a length code of 15. These relations
are summarized in the second table.
The third table lists the maximum sizes of the
page table and the increments in which the size of
the page table can be controlled. Real Storage Address
Page Address Size of Page Bit Positions in Page-Table 2K 4K Size of Segment
(Bvtes)
64K
1M Size of
Segment Page
Entry 0-12 0-11 Segment I ndex Field Size (Bits)
8
4
Page I ndex Field (Bytes) Size (Bits)
64K 2K 5
64K 4K 4
1M 2K 9
1M 4K 8
Summary of DAT Formats
68 System/370 Principles of Operation No. of Bits
13
12
Number of Addressable
Segments
256
16
Number of Pages in
Segment
32
16
512
256
Byte Index Bit Positions in Logical Address No. of Bits
21-31 20-31 Maximum Segment Table Size Usable Length
(Bytes) Code 1,024 15
64 0 Maximum Page Table Size Usable Length
(Bytes) Code
64 15
32 15 1,024 15
512 15
11
12 Table Increment (Bytes)
64
64 Table Increment (Bytes)
4
2
64
32