exception to be recognized, results are unpredicta­
ble. Furthermore, it is unpredictable whether an
interruption for the access exception occurs. In the
case of ED and EDMK, this situation can occur also
because of overlapping operands.
This case is an exception to the general rule that
the operation is nullified on segment-translation and
page-translation exceptions and is suppressed on a
translation-specification exception and on an ad­
dressing exception caused by an invalid address of a
table entry. When, in this case, an interruption for a
segment-translation or page-translation occurs, the
instruction address in the old PSW points to the in­
struction causing the exception even though partial
results have been stored. PTogranrumdng An access exception is indicated as part of the execu­
tion of the instruction with which the exception is
associated. In particular, the exception is not recog­
nized when the CPU has made an attempt to fetch
from the inaccessible location or otherwise has de­
tected the access exception, but a branch instruction
or an interruption changes the instruction sequence
such that the instruction is not executed.
The following are some specific storage refer­
ences where access exceptions, including store pro­
tection when applicable, are recognized even if the
operation could be completed without the use of the
inaccessible part of the operand: • Fetching the operand of TEST UNDER MASK
with a zero mask. • Fetching parts of operands of algebraic compare
instructions (C and CH). • Fetching parts of operands of floating-point
instructions. • References to the first-operand location of deci­
mal instructions when the second operand in
addition and subtraction is zero or in multipli­
cation and division is one. • Storing the pattern character in an edit opera­
tion when the pattern character remains un­
changed. • Storing during SHIFT AND ROUND DECI­
MAL when no shifting or rounding takes place. • Storing during move operations when the first­
and second-operand locations coincide. • Storing the first operand of OR (01 and OC) when the corresponding second-operand byte
is zero, as well as the analogous cases for AND
and EXCLUSIVE OR. • Storing the first operand of TRANSLATE
when the argument and function bytes are the
same.
Page ofGA22-7000-4 Revised September 1,1975
By TNL: GN22-0498
With a nonzero mask in INSERT CHARAC­
TERS UNDER MASK, COMPARE LOGICAL CHARACTERS UNDER MASK, and STORE CHARACTERS UNDER MASK, access exceptions
are indicated only for the extent of the storage oper­
and designated by the mask. In MOVE LONG or COMPARE LOGICAL LONG, no exceptions are
recognized for any operand having a length of zero.
Handling of Multiple
Program-Interruption Conditions
Except for program events, only one program­
interruption condition is indicated with a program in -
terruption. The existence of one condition, however,
does not preclude the existence of other condi-
tions. When more than one program-interruption
condition exists, only the condition having the high­
est priority is identified in the interruption code.
When two conditions exist of the same priority, it
is unpredictable which is indicated. In particular, the
priority of access exceptions associated with the two
parts of an operand that crosses a page or a protec­
tion boundary is unpredictable and is not necessarily
related to the sequence specified for the access of
bytes within the operand.
The type of ending which occurs (nullification,
suppression, or termination) is that which is defined
for the type of exception that is indicated in the in­
terruption code. However, if a condition is indicated
which permits termination, and another condition
also exists which would cause either nullification or
suppression, then the unit of operation is suppressed.
The table "Priorities of Access Exceptions" lists
the priorities of access exceptions for a single access.
The table "Priorities of Program Interruption Condi­ tions" lists the priorities of all program-interruption
conditions other than program events. All exceptions
associated with references to storage for a particular
instruction halfword or a particular operand byte are
grouped as a single entry called "access." Thus, the
first table specifies which of several exceptions that
are encountered in the access of a particular portion
of an instruction, or in any particular access associat­
ed with an operand, has highest priority, and the
latter table specifies the priority of this condition in
relation to other conditions detected in the opera­
tion.
The relative priorities of any two conditions can
be found by comparing the priority numbers within a
table from left to right until a mismatch is found. If
the first inequality is between numeric characters,
the two conditions are either mutually exclusive, or,
if both can occur, the condition with the smaller
number is indicated. If the first inequality is between
alphabetic characters, the two conditions are not
Interruptions 83

1. Translation-specification exception due to invalid page size or segment size
designation or due to a one in bit position 10 of control register O. 2. Se'gment-translation exception due to segment-table entry being outside table.
3. Addressing exception due to segment-table entry being outside main storage of
in:stallation.
4. SElgment-translation exception due to I bit having the value one.
5. Translation-specification exception due to invalid ones in segment-table entry.
6. exception due to page-table entry being outside table.
7. Addressing exception due to page-table entry being outside main storage of
installation.
8. Pclge-translation exception due to I bit having the value one.
9. Tlranslation-specification exception due to invalid ones in page-table entry. 10. Addressing exception due to instruction or operand location outside main
storage of installation.
11. Pmtection exception due to attempt to access a protected instruction.or operand location. The acc:ess exceptions are listed in the order of descending priorities.
Priorities of Access Exceptions
exclusive, and it is unpredictable which is indicated
when both occur. The second instruction halfword is accessed only
if bits 0-1 of the instruction are not 00. The third instruction half word is accessed only if bits 0-1 of
the instruction are 11.
Supervisor-Call Interruption
The supervisor-call interruption occurs as a result of
the execution of the instruction SUPERVISOR CALL. The CPU cannot be disabled for the inter­
ruption, and the interruption occurs immediately
upon the execution of the instruction.
The supervisor-call interruption causes the old PSW to be stored at location 32 and a new PSW to
be fet.ched from location 96.
The contents of bit positions 8-15 of SUPERVI­ SOR CALL are placed in the low-order byte of the
interruption code. The high-order byte of the inter­
ruption code is set to zero. The instruction-length
code is 1, unless the instruction was executed by
means of EXECUTE, in which case the code is 2.
When the old PSW specifies the BC mode, the
interruption code and instruction-length code appear
in the old PSW; when the old PSW specifies the EC
mode, the interruption code is placed at locations
138-Jl39, the instruction-length code is placed in bit
positions 5 and 6 of the byte at location 137, with
84 System/370 Principles of Operation
the other bits set to zero, and zeros are stored at
location 136.
Programming Note
The name "supervisor call" indicates that one of the
major purposes of the interruption is the switching
from problem to supervisor state. This major pur­
pose does not preclude the use of this interruption
for other types of status switching.
The interruption code may be used to convey a
message from the calling program to the supervisor.
External Interruption
The external interruption provides a means by which
the CPU responds to various signals originating ei­
ther from within or from outside of the system.
An external interruption causes the old PSW to be
stored at location 24 and a new PSW to be fetched
from location 88.
The source of the interruption is identified in the
interruption code. When the old PSW specifies the
BC mode, the interruption code is placed in bit posi­
tions 16-31 of the old PSW, and the instruction­
length code is unpredictable. When the old PSW specifies the EC mode, the interruption code is
placed at locations 134-135.
Additionally, in both the BC and EC modes, for
some conditions a 16-bit processor address is associ-