Facilities are provided for holding a separate
malfunction-alert request pending in the receiving CPU for each other configured CPU. Configuring a CPU out of the system does not generate a
malfunction-alert condition.
The condition is indicated by an external­
interruption code of 1200 (hex). The processor
address of the CPU that generated the condition is
stored at locations 132-133.
The subclass mask bit is located in bit position 16
of control register O. This bit is initialized to zero.
Emergency Signal
An interruption request for emergency signal is gen­
erated when the CPU accepts the emergency-signal
order specified by a SIGNAL PROCESSOR instruc­
tion addressing this CPU. The instruction may have
been executed by this CPU or by another CPU con­
figured to this CPU. The request is preserved and
remains pending in the receiving CPU until it is
cleared. The pending request is cleared when it caus­
es an interruption and by CPU reset.
Facilities are provided for holding a separate
emergency-signal request pending in the receiving CPU for each configured CPU, including the receiv­
ing CPU itself.
The condition is indicated by an external­
interruption code of 1201 (hex). The processor
address of the CPU that issued the SIGNAL PRO­ CESSOR instruction is stored at locations 132-133.
The subclass mask bit is located in bit position 17
of control register o. This bit is initialized to zero.
External Call
An interruption request for external call is generated
when the CPU accepts the external-call order speci­
fied by a SIGNAL PROCESSOR instruction ad­
dressing this CPU. The instruction may have been
executed by this CPU or by another CPU configured
to this CPU. The request is preserved and remains
pending in the receiving CPU until it is cleared. The
pending request is cleared when it causes an inter­
ruption and by CPU reset. Only one external-call request, along with the
processor address, may be held pending in a CPU at
a time.
The condition is indicated by an external­
interruption code of 1202 (hex). The processor
address of the CPU that issued the SIGNAL PRO­ cEssoR instruction is stored at locations 132-133.
The subclass mask bit is located in bit position 18
of control register o. This bit is initialized to zero.
Time-or-Day Clock Sync Check
The time-of-day (TOD) clock sync check condition
indicates that more than one TOD clock exists in the
configuration, and that the low-order 32 bits of the
clocks are not running in synchronism.
An interruption request for TOD clock sync
check exists when the clock accessed by this CPU is
running, the clock accessed by any other CPU con­
figured to this CPU is running, and bits 32-63 of the
two clocks do not match. ,When a clock enters the
running state, or a running clock is added to the
configuration, a delay of up to 1.048576 seconds (2
20 microseconds) may occur before the mismatch
condition is recognized.
When only two clocks are in the configuration
and either or both of the clocks are in the error,
stopped, or not-operational state, it is unpredictable
whether a TOD clock sync check condition is recog­
nized, and, if it is recognized, it may continue to
persist up to 1.048576 seconds after both clocks
have been running with low-order bits matching.
However, in this case, the condition does not persist
if the two CPU s are configured apart.
When more than one CPU shares a TOD clock,
only the CPU with the smallest processor address
among those sharing the clock indicates a sync­
check condition associated with that clock.
If the condition responsible for the request is re­
moved before the request is honored, the request
does not remain pending, and no interruption occurs.
Conversely, the request is not cleared by the inter­
ruption, and, if the condition persists, more than one
interruption may result from a single occurrence of
the condition.
The condition is indicated by an external­
interruption code of 1003 (hex). In the EC mode,
zeros are stored at locations 132-133.
The subclass mask bit is located in bit position 19
of control register O. This bit is initialized to zero.
Clock Comparator
An interruption request for the clock comparator
exists whenever either of the following conditions is
met:
1. The time-of-day clock is running, and the value
of the clock comparator is less than the value
in the compared portion of the time-of -day
clock, both comparands being considered bina­
ry unsigned quantities.
2. The clock comparator is installed, and the tim.e­
of-day clock is in the error state or not opera­
tional.
If the condition responsible for the request is re­
moved before the request is honored, the request
does not remain pending, and no interruption occurs.
Interruptions 87

Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
Conversely, the request is not cleared by the inter­
ruption, and, if the condition persists, more than one
interruption may result from a single occurrence of
the condition. The condition is indicated by an external­
interruption code of 1004 (hex). In the Ee mode,
zeros are stored at locations 132-133. The submask bit is located in bit position 20 of
control register O. This bit is initialized to zero. CPU Timer
An interruption request for the CPU timer exists whenever the CPU timer value is negative (bit 0 of
the CPU timer is one). If the value is made positive
before the request is honored, the request does not
remain pending, and no interruption occurs. Con­
versely, the request is not cleared by the interrup­
tion, and, if the condition persists, more than one
interruption may occur from a single occurrence of
the condition.
The condition is indicated by an external­
interruption code of 1005 (hex). In the EC mode,
zeros are stored at locations 132-133.
The submask bit is located in bit position 21 of
control register O. This bit is initialized to zero.
Input/Output Interruption
The input/output (I/O) interruption provides a
means by which the CPU responds to conditions in I/O devices and channels.
An I/O interruption causes the old PSW to be
stored at location 56, a channel status word to be
stored at location 64, and a new PSW to be fetched
from location 120. Upon detection of equipment
errors, additional information may be stored in the
form of a limited channel logout at location 176 and
in the form of an I/O extended logout starting at the
location designated by the contents of locations 173-
175.
When the old PSW specifies the BC mode, the
interruption code in PSW bit positions 16-31 identi­
fies the channel and device causing the interruption:
the channel address appears in the high-order eight
bit positions and the device address in the low-order
eight. The·instruction-Iength code is unpredictable.
When the old PSW specifies the EC mode, the de­
vice address is placed at location 187, the channel addre:ss at location 186, and zeros are stored at loca­
tion 185. An I/O interruption can occur only while the CPU is enabled for interruption by the channel pre­
senting the request. Whether the CPU is enabled for
interruption by a channel is controlled by mask bits
88 System/370 Principles of Operation
in the PSW and by channel masks in control register
2, and the method of control depends on whether
the current PSW specifies the BC or EC mode.
Channel mask bits are located in control register
2 starting at bit position 0 and extending for as many
contiguous bit positions as the number of channels
provided. The assignment is such that a bit is as­
signed to the channel whose address is equal to the
position of the bit in control register 2. Channel­
mask bits for installed channels are initialized to one.
The state of channel mask bits for unavailable chan­
nels is unpredictable.
When the current PSW specifies the BC mode,
interruptions from channels 6 and up are controlled
by the I/O mask bit, PSW bit 6, in conjunction with
the corresponding channel mask bit: the channel can
cause an interruption only when the I/O mask is one
and the corresponding channel mask is one. Interrup­
tions from channels 0-5 are controlled by channel
masks 0-5 in the PSW; an interruption can occur
only when the mask corresponding to the channel is
one. In the BC mode, bits 0-5 in control register 2
do not participate in controlling I/O interruptions;
they are, however, preserved in the control register.
When the current PSW specifies the EC mode,
each channel is controlled by the I/O mask bit and
the corresponding channel mask bit in control regis­
ter 2: the channel can cause an interruption only
when the I/O mask bit ts one and the corresponding
channel mask bit is one.
When the CPU becomes enabled for a pending
I/O-interruption condition, the interruption occurs
at the completion of the instruction execution or
interruption that causes the enabling.
A request for an I/O interruption may occur at
any time, and more than one request may occur at
the same time. The requests are preserved and re­
main pending in channels or devices until accepted
by the CPU. Priority is established among requests
so that only one interruption request is processed at
a time. For more details
1 see the section "Input/Output Interruptions" in the chapter on I/O operations.
Restart
The restart interruption PFovides a means for the
operator or another CPU to invoke the execution of
a program. The CPU cannot be disabled for this
interruption.
A restart interruption causes the old PSW to be
stored at main-storage location 8 and a new PSW to
be fetched from location O. In the BC mode, the
instruction-length code in the PSW is unpredictable,