Page of GA22-70004 Revised September 1, 1975
By TNL: GN22-0498
Multiprocessing
Contents
Shared Main Storage
Prefixing. . . .
CPU Signaling and Response Orders . . . . .
Conditions Determining Response . . . . . . .
95
95
97
97
98
98
99
Conditions Precluding Interpretation of the Order Code
Status Bits TOO Clock Synchronization
CPU Address Identification
The multiprocessing feature provides for the inter­
connection of CPUs, via a common main storage, in
order to enhance system availability and to share
data and resources. The multiprocessing feature in­
cludes the following facilities: • Shared main storage • Prefixing • CPU signaling and response • TOD-clock synchronization
Associated with these facilities are four extensions
to external interruption (external call, emergency
signal, TOD clock sync check, and malfunction
alert), which are described in the chapter
"Interruptions"; control-register positions for the
TOD-clock-sync-control bit and for the masks for
the four external-interruption conditions, which are
listed in "Control Registers" in the chapter "System
Control"; and the instructions SET PREFIX, SIG­
NAL PROCESSOR, STORE CPU ADDRESS, and STORE PREFIX, which are described in the chapter
"System-Control Instructions."
When the CPU is equipped with the multiprocess­
ing feature, certain additional functions are provided
as part of the system console. These functions per­
tain to the following controls, which are described in
the chapter "System Console": configuration con­
trols, enable-system-clear key, load key, system­
reset key, and TOD-clock key.
Channels in a multiprocessing system are associat­
ed with a particular CPU. Only one CPU can initiate 110 operations at a channel, and all interruption
conditions are directed to that CPU. Shared Main Storage
The shared-main-storage facility permits more than
one CPU to have access to common main-storage
locations. All CPU s having access to a common 101 101 main-storage location have access to the entire 2,048-byte block containing that location and to the
associated key in storage. All CPUs refer to a shared­
main-storage location using the same absolute ad­
dress.
Prefixing
When the multiprocessing feature is installed in a CPU, most addresses associated with storage refer­
ences by the CPU are processed by a mechanism
called "prefixing." All addresses subject to this pro­
cessing are referred to as "real" addresses. Storage
addresses which are not subject to this processing,
and all addresses that have been processed, whether
or not they are changed, are referred to as
"absolute" addresses.
As a result of the processing to form the absolute
address, real addresses 0-4095 are interchanged with
the 4,096 addresses of the block that begins at the
address identified in the prefix register. All other real
addresses remain unchanged.
The real addresses 0-4095 include the addresses
of the assigned storage locations that are implicitly
generated by the CPU and channels, and include the
addresses that can be specified by the program with­
out the use of a base address or an index. Prefixing
provides the ability to reassign this block of real
locations for each CPU to a different block in abso­
lute main storage, thus permitting more than one CPU sharing main storage to operate concurrently
with a minimum of interference,cespecially in the
processing of interruptions.
Because the prefixing mechanism interchanges
the real addresses, each CPU can access all of abso­
lute main storage, including the first 4,096 bytes and
the assigned locations for another CPU. MUltiprocessing 95

Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 The relationship between, real and absolute ad­
dresses is graphically depicted in the figure
"Relationship Between Real and Absolute Addresses. " The prefix is a 12-bit quantity located in the pre-
fix register. The register has the following format: The contents of the register can be set and in­ specte:d by the privileged instructions SET PREFIX and STORE PREFIX, respectively. On setting, bits
corresponding to bit positions 0-7 and 20--31 of the
prefix register are ignored. On storing, zeros are
provided for these bit positions. The prefix register is initialiized to zero. PreJixing is applied to all references to main stor­
age and to keys in storage, except for references by
a CPU to the permanently assigned storage locations
during performance of the store-status function, and
except for references by a channel to extended­
logout locations, to 110 data, to indirect-data-
address words, and to CCWs. When dynamic ad­
dress translation is specified, prefixing is applied
after the address has been translated by the dynamic­
address-translation mechanism. When installed,
prefixing is always active and is not subject to any
mode control.
When prefixing is applied, the storage address is
translated as follows:
1. Bits 8-19 of the storage address, if all zeros,
are replaced with bits 8-19 of the prefix.
2. Bits 8-19 of the storage address, if equal to bits
8-19 of the prefix, are replaced with all zeros.
3. Bits 8-19 of the storage address, if not all zeros
and not equal to bits 8-19 of the prefix, remain
unchanged.
In all cases, bits 20-31 of the storage address re­
main unchanged.
Only the address presented to storage is translat­
ed by prefixing. The contents of the source of the
address remain unchanged.
The distinction between real and absolute ad­
dresses is made even when prefixing is not installed I I I Kf-----If-.No Change-r------+---- I I I CJ, I I I I I I /Address 4096 LAddress I \ ; I L __________ I Address I 4096 I L ________ -.J o Real Addresses
for CPU A Absolute Addresses CD Rlaal addresses in which the high·order 12 bits are equal to the prefix for this CPU (A or B). (3) Absolute addresses of the block that contains, for this CPU (A or B), the assigned locations in real storage.
Relationship Between Real and Absolute Addresses
96 System/370 Principles of Operation ...-Address 4096 ...-Address o Real Addresses
for CPU B