ured to the CPU being reset. The reset operation is
not necessarily completed during the execution of
the SIGNAL PROCESSOR instruction.
Stop and Store Status: The addressed CPU per­
forms the stop function, followed by the store··status function (see "Stopped and Operating States" and "Store Status" in the chapter "System The CPU does not necessarily complete the opera­
tion, or even enter the stopped state, during the exe­
cution of the SIGNAL PROCESSOR instruction.
Initial Mricroprogram Load (lMPL): The addressed CPU performs initial program reset and then initi­
ates the initial-microprogram-Ioad function. The
latter funetion is the same as that which is performed
as part of manual initial microprogram loading. If the
initial-mic:roprogram-Ioad function is not provided
on the addressed CPU, the order code is treated as
unassigned and invalid. The operation is not neces­
sarily completed during the execution of the SIG­ NAL PROCESSOR instruction.
Initial CPU Reset: The addressed CPU performs
initial CPU reset (see "Resets" in the chapter "System Control"). The execution of the reset does
not affect other CPUs and does not cause any chan­
nels, including those configured to the addressed CPU, to be reset. The reset operation is not neces­
sarily completed during the execution of the SIG­ NAL PROCESSOR instruction. CPU RE'Set: The addressed CPU performs CPU reset (see "Resets" in the chapter "System Con­
trol"). The execution of the reset does not affect
other CPUs and does not cause any channels, in­
cluding those configured to the addressed CPU, to
be reset. The reset operation is not necessarily com­
pleted during the execution of the SIGNAL PRO­ CESSOR instruction. Determining Response
Conditions Precluding Interpretation of the Order Code
The following situations determine the initiation of
the order. The sequence in which the situations are
listed is the order of priority for indicating concur­
rently existing situations:
1. The access path to the addressed CPU is busy
because a concurrently issued SIGNAL PROCESSOR instruction is using the CPU­ signaling-and-response facility. The concur­
rently issued instruction mayor may not have
been issued by or to the addressed CPU and
98 System/370 Principles of Operation
mayor may not have been issued to this CPU. The order is rejected. Condition code 2 is set.
2. The addressed CPU is not operational, that is,
the addressed CPU is not installed, is not con­
figured to the issuing CPU, or is in certain
customer-engineer test modes, or does not
have its power on. The order is rejected. Con­
dition code 3 is set.
3. One of the following conditions exists at the
addressed CPU: a. A previously issued start, stop, restart, or
stop-and-store-status order has been accept­
ed by the addressed CPU, and execution of
the order has not yet been completed.
b. A manual start, stop, restart, or store-status
function has been initiated at the addressed CPU, and the operation has not yet been
completed.
c. A manual initial-pro gram-load function has
been initiated at the addressed CPU, and
the reset portion, but not the program load
portion, of the operation has been complet­
ed.
If the currently specified order is a sense,
external call, emergency signal, start, stop,
restart, or stop and store status, the order is
rejected, and condition code 2 is set. If the
currently specified order is an IMPL, one of
the reset orders, or an unassigned or not­
implemented order, the order code is inter­
preted as described in the section "Status Bits."
4. One of the following conditions exists at the
addressed CPU: a. A previously issued initial-program-reset,
program-reset, IMPL, initial-CPU-reset, or CPU-reset order has been accepted by the
addressed CPU, and execution of the order
has not yet been completed.
b. A manual reset or IMPL function has been
initiated at the addressed CPU, and the
function has not yet been completed. The
term "manual reset function" includes the
reset portion of IPL. If the currently specified order is a sense,
external call, emergency signal, start, stop,
restart, or stop and store status, the order is
rejected, and condition code 2 is set. If the
currently specified order is an IMPL, one of
the reset orders, or an unassigned or not­
implemented order, either the order is re­
jected and condition code 2 is set or the or-

der code is interpreted as described under
the heading "Status Bits. " When any of the conditions described in 3 and 4
exists, the addressed CPU is referred to as "busy." Busy is not indicated if the addressed CPU is in the
check-stop state or when the operator-intervening
condition exists. A GPU-busy condition is normally
of short duration; however, the conditions described
in item 3 may last indefinitely because of an unend­
ing series of interruptions or because of an invalid
address in the prefix register. In this situation, how­
ever, the CPU does not appear busy to any of the
reset orders or to IMPL.
Status Bits
Eight status conditions are defined whereby the issu­
ing and addressed CPUs can indicate their response
to the designated order. The status conditions and
their bit positions in the general register designated
by the Rl field of the SIGNAL PROCESSOR in­
struction are as follows:
Bit Position Status Condition 0 Equ i pment check 1·23 Unassigned; zeros stored
24 External-call pending
25 Stopped
26 Operator intervening
27 Check stop
28 Not ready
29 Unassigned; zero stored 30 Invalid order
31 Receiver check
The status condition assigned to bit position 0 is
generated by the CPU executing the SIGNAL PROCESSOR instruction. The status conditions
assigned to bit positions 24-31 are generated by the
addressed CPU.
When the access path to the addressed CPU is
not busy and the addressed CPU is operational and
does not indicate busy to the currently specified
order, the addressed CPU presents its status to the
issuing CPU. These status bits are of two types: • Status bits 24-28 indicate the presence of the
corresponding conditions in the addressed CPU at the time the order code is received.
Except in response to the sense order, each
condition is indicated only when the condition
precludes the successful execution of the desig­
nated order. In the case of sense, all existing
status conditions are indicated; the operator­
intervening and not-ready conditions each are
indicated if these conditions preclude the exe­
cution of any installed order. • Status bits 30 and 31 indicate that the corre­
sponding conditions were detected by the ad­
dressed CPU during reception of the order.
If the presented status is all zeros, the addressed CPU has accepted the order, and condition code 0 is
set at the issuing CPU; if the presented status is not
all zeros, the addressed CPU has rejected the order,
the presented status is stored at the issuing CPU in
the general register designated by the Rl field of the SIGNAL PROCESSOR instruction, zeros are stored
in bit positions 0-23 of the register, and condition
code 1 is set.
When the equipment-check condition exists, bit 0 of the general register designated by the Rl field of
the SIGNAL PROCESSOR instruction is set to one,
bits 1-23 are set to zeros, and the contents of bit
positions 24-31 are unpredictable. In this case, con­
dition code 1 is set independently of whether the
access path to the addressed CPU is busy and inde­
pendently of whether the addressed CPU is not op­
erational, is busy, or has presented zero status.
The status conditions are defined as follows:
Equipment Check: This condition exists when the CPU executing the instruction detects equipment
malfunctioning that has affected only the execution
of this instruction and the associated order. The or­
der code mayor may not have been transmitted, and
mayor may not have been accepted, and the status
bits provided by the addressed processor may be in
error.
External Call Pending: This condition exists when
an external-call interruption condition is pending in
the addressed CPU because of a previously issued SIGNAL PROCESSOR instruction. The condition
exists from the time an external-call order is accept­
ed until the resultant external interruption has been
completed. The condition may be due to the issuing CPU or another CPU. The condition, when present,
is indicated only in response to sense and to external
call.
Stopped: This condition exists when the addressed CPU is in the stopped state. The condition, when
present, is indicated only in response to sense.
Operator Intervening: This condition exists when
the addressed CPU is executing certain operations
initiated from the console or the remote operator
control panel. The particular manually initiated op­
erations that cause this condition to be present de­
pend on the model and on the order specified. This
condition, when present, can be indicated in re­
sponse to all orders. Operator intervening is indicat-
Multiprocessing 99