ed in response to sense if the condition is present
and precludes the acceptance of any of the installed
orders. The condition may also be indicated in re­
sponse to unassigned or uninstalled orders.
Check Stop: This condition exists when the ad­
dressed CPU is in the check-stop state. The condi­
tion, when present, is indicated only in response to
sense, external call, emergency signal, start, stop,
restart, and stop and store status. The condition may
also be indicated in response to unassigned or unin-
stalled orders. . .
Not Ready: This condition exists when the ad­
dressed CPU uses reloadable control storage to per­
form an order and the required microprogram is not
loaded. The not-ready condition may be indicated in
response to all orders except IMPL.
Invalid Order: This condition exists during the com­
munications associated with the execution of SIG­ NAL PROCESSOR when the addressed CPU de­
codes an unassigned or uninstalled order code.
Receiver Check 1= I nval id Order
Not Ready
l Check Stop Operator Intervening #
Stopped -
External Call Pending
Sense X X X X X
External Celli X 0 X X X
Emergency Signal 0 0 X X X
Start 0 0 X X X
Stop 0 0 X X X
Restart 0 0 X X X Initial Progrram Reset 0 0 X 0 X
Program Reset 0 0 X 0 X
Stop and Store Status 0 0 X X X IMPL* 0 0 X 0 0 Initial CPU Reset* 0 0 X 0 X CPU 0 a X 0 X
Unassigned Order 0 0 X O/X X
Explanation: 0 0 0 0 0 0 0 0 0 0 0 0 Receiver Check: This condition exists when the
addressed CPU detects malfunctioning of equipment
during the communications associated with the exe­
cution of SIGNAL PROCESSOR. When this condi­
tion is indicated, the order has not been initiated
and, since the malfunction may have affected the
generation of the remaining receiver status bits,
these bits are not necessarily valid. A machine-check
condition mayor may not have been generated at
the addressed CPU. The following chart summarizes which status con­
ditions are presented to the issuing CPU in response
to each order code.
If the presented status bits are all zeros, the order
has been accepted, and the issuing processor sets
condition code O. If one or more ones are presented,
the order has been rejected, and the issuing proces­
so'r stores the status in the general register specified
by the Rl field of the SIGP instruction and sets
condition code 1.
Programming Notes
A CPU can obtain the following functions by
addressing SIGNAL PROCESSOR to itself:
1. Sense indicates whether an external-call condi­
tion is pending.
X
X
X
X
X
X
X
X
X
X
X
X
X
o A zero is presented in this bit position regardless of the current state of this condition.
1 A one is presented in this bit position. X A zero or a one is presented in this bit position, reflecting the current state of the corresponding condition. O/X Eithl3r a zero or the current state of the corresponding condition is indicated.
# The current state of the condition may depend on the order code that is being interpreted. f If a ()ne is presented in the receiver-check bit position, the values presented in the other bit positions are not
necessarily valid. If the order code is implemented, use the line entry for the order code; if the order code is not implemented, use
the line entry labeled "Unassigned Order." 100 System/370 Principles of Operation

2. External call and emergency signal cause the
corresponding interruption conditions to be
generated. External call can be rejected be­
cause of a previously generated external-call
condition.
3. Start sets condition code ° and has no other
effect.
4. Stop causes the CPU to set condition code 0, take pending interruptions for which it is ena­
bled, and enter the stopped state.
S. Restart provides a means to store the current PSW. Two CPUs can simultaneously execute SIGNAL PROCESSOR instructions, with each CPU address­
ing the other. When this occurs, one CPU, but not
both, can find the access path busy because of the
transmission of the order code or status bits associat­
ed with the SIGNAL PROCESSOR instruction that
is being executed by the other CPU. Alternatively,
both CPUs can find the access path available and
transmit the order codes to each other. In particular,
two CPUs can simultaneously stop, restart, or reset
each other.
TOO Clock Synchronization
In an installation with more than one CPU, depend­
ing on the model, each CPU may have a separate
time-of -day clock, or more than one CPU may share
a clock. In all cases, each CPU accesses a single
clock. A configuration change does not affect the
value in any of the clocks or which clock a CPU accesses.
When more than one time-of-day clock exists in a
configured system, the stepping rates are synchro­
nized such that all time-of-day clocks in the configu­
ration are incremented at the exact same rate. The CPU timer in each CPU is also decremented at this
same rate.
The TOD-clock-synchronization facility provides
functions that make it possible to write a single
model-independent supervisor clock-synchronization
program which can handle systems with a single
time-of-day clock or with multiple clocks. Addition­
ally, the facility, in conjunction with the supervisor
clock-synchronization program, provides, in effect,
only one clock in a multiprocessing system, so that,
to all programs storing the clock, it appears that all CPUs read the same clock.
The synchronization is provided by a mechanism
which causes a stopped clock to start incrementing in
response to a signal from another clock and which
checks whether the low-order 32 bits of all clocks in
the configuration are stepped at the same time.
Lack of synchronization is signaled by an external
interruption indicating the TOD-clock-sync-check
condition. The synchronization is under control of
the TOD-clock-sync-control bit in control register 0, bit position 2. See "Time-of-Day Clock Sync Check" in the chapter "Interruptions" and "Time-of­ Day Clock" in the chapter "System Control." Programming Note . A stopped clock, with the TOD-clock-sync-control
bit set to one, starts when bits 32-63 of any running
clock in the configuration are incremented to zero.
This permits the program to synchronize all clocks to
any particular clock without requiring special opera­
tor action to select a "master clock" as the source of
the clock synchronization pulses. The supervisor
clock-synchronization program must check for syn­
chronization of high-order bits and assist in syn­
chronizing clocks by communicating the high-order
bit values and setting them in the clocks to be syn­
chronized. CPU Address Identification
Each CPU in a multiprocessor installation is as­
signed a unique address. The CPU is designated by
specifying this address in the processor address field
of a SIGNAL PROCESSOR instruction. The CPU signaling a malfunction alert, emergency signal, or
external call is identified by storing this address in
the processor-address field with the interruption.
The CPU address is assigned during system installa­
tion and is not changed as a result of configuration
changes. The program can determine the address of
the CPU by means of the instruction STORE CPU ADDRESS. Multiprocessing 101