Name Mnemonic Characteristics Code DIAGNOSE M DM 83 INSERT PSW KEY IPK S PK M R 8208 INSERT STORAGE KEY ISK RR M A1 SP R 09 LoAD CONTROL LCTL RS M A SP 87
LOAD PSW LPSW S L M A SP $ 82
LOAD REAL ADDRESS LRA RX C
TR M A2 R
81
PURGE TIL8 PTL8 S TR M $ 820D READ DIHECT RDD SI DC M A $ ST 85
RESET RI:FERENCE BIT RR8 S C
TR M A1 8213
SET CLOCK SCK S C
M A SP 8204 SET CLOCK COMPARATOR SCKC S CK M A SP 8206 SET CPU TIMER SPT S CK M A SP 8208 SET PREFIX SPX S MP M A SP $ 8210 SET PSW IKEY FROM ADDRESS SPKA S PK M 820A SET STOnAGE KEY SSK RR M A1 SP 08 SET SYSTEM MASK SSM S M A SO 80 SIGNAL PROCESSOR SIGP RS C
MP M $ R
AE STORE CLOCK COMPARATOR STCKC S CK M A SP ST 8207 STORE CONTROL STCTL RS M A SP ST 86 STORE CPU ADDRESS STAP S MP M A SP ST 8212 STORE CPU ID STIDP S M A SP ST 8202 STORE CPU TIMER STPT S CK M A SP ST 8209 STORE PHEFIX STPX S MP M A SP ST 8211 STORE TI-IEN AND SYSTEM MASK STNSM SI TR M A ST AC
STORE THEN OR SYSTEM MASK STOSM SI TR M A ST AD WRITE DIRECT WRD SI DC M A $ 84 Explanation: A exceptions PK PSW-key-handling feature
A1 exceptions only R PER general-register-alteration event
A2 and translation-specification exceptions only RR RR instruction format
C
Condition code is set RS RS instruction format
CK CPU-ti mer and clock-comparator feature RX RX instruction format
DC Direct-control feature S S instruction format
DM Depending on the model, DIAGNOSE may generate SI SI instruction format
various program exceptions and may change the SO Special-operation exception
condition code. SP Specification exception
L New Icondition code loaded ST PER storage-alteration event
M Privil,eged-operation exception TR Translation feature
MP Multiprocessing feature $ Causes serialization
System-Control-Instruction Summary follow the rule that programming errors are distin-Insert PSW Key
guished from equipment errors. Improper use of DIAGNOSE may result in false indi- IPK [S] cations or may cause actual machine malfunctions to
be ignored. It may also alter other aspects of system 8208 operation, including instruction execution and chan- 0 16 31
nel operation, to an extent that the operation does
not comply with that specified in this manual. As a The four-bit protection key of the current PSW is
result of the improper use of DIAGNOSE, the sys-inserted into bit positions 24-27 of general register
tern may be left in such a condition that the power-2. Bits 0-23 of general register 2 remain unchanged,
on reset or initial-microprogram-Ioading function and bits 28-31 are set to zeros. Bits 16-31 of the
must be performed. instruction are ignored. 104 System/370 Principles of Operation

Condition Code: The code remains unchanged.
Program Exceptions: Operation (if the PSW-key-handling feature is not
installed)
Privileged operation
Insert Storage Key ISK [RR]
o 8 12 15
The key in storage associated with the block that is
addressed by the contents of the general register
designated by the R2 field is inserted in the general
register designated by the Rt field.
Bits 8-20 of the register designated by the R2
field designate a block of 2,048 bytes in real main
storage. Bits 0-7 and 21-27 of the register are ig­
nored. Bits 28-31 of the register must be zeros; oth­
erwise, a specification exception is recognized, and
the operation is suppressed.
The address designating the storage block, being a
real address, is not subject to dynamic address trans­
lation. Hence, the reference to the key cannot cause
segment-translation, page-translation, and
translation-specification exceptions to be recognized,
and an addressing exception can be caused only by
an invalid storage-block address (as contrasted to an
invalid address of a table entry). The reference to
the key is not subject to a protection exception.
The execution of the instruction depends on the
mode of operation. When the PSW specifies the
extended-control mode, the complete seven-bit key
is inserted into bit positions 24-30 of the register
designated by the Rt field, with bit 31 set to zero.
When the PSW specifies the basic-control mode, bits 0-4 of the key are placed in bit positions 24-28 of .the register, with bits 29-31 of the register set to
zeros. The contents of bit positions 0-23 of the regis­
ter remain unchanged.
Condition Code: The code remains unchanged.
Program Exceptions:
Privileged operation
Access (addressing for operand access only, oper­
and 2)
Specification
Load Control
LCTL Rl,R3,D2(B2) [RS] B7 I R, I R3 I B2 I D2 I 0 8 12 16 20 31
The set of control registers starting with the control
register designated by the R t field and ending with
the control register designated by the R3 field is
loaded from the locations designated by the second­
operand address.
The storage area from which the contents of the
control registers are obtained starts at the location
designated by the second-operand address and con­
tinues through as many storage words as the number
of control registers specified. The control registers
are loaded in ascending order of their addresses,
starting with the control register designated by the
Rt field and continuing up to and including the con­
trol register designated by the R3 field, with control
register 0 following control register 15. The second
operand remains unchanged.
An attempt is made to fetch the operand from
main storage for each of the designated control reg­
isters, regardless of whether the facility requiring the
presence of the control register is installed. Whenev­
er the storage reference causes an access exception,
the exception is indicated.
The second operand must be designated on a
word boundary; otherwise, a specification exception
is recognized, and the operation is suppressed.
Condition Code: The code remains unchanged.
Program Exceptions:
Privileged operation
Access (fetch, operand 2)
Specification
Programming Note
To ensure that presently written programs run when
new facilities using additional control register posi­
tions are installed, only zeros should be loaded in
unassigned control register positions.
Load PSW LPSW 82 J
o 8 16 20 31
System-Control Instructions 105