An attempt is made to store each of the designat­
ed control registers, regardless of whether the facility
requiring the presence of the control register is in­
stalled. \Vhenever the storage reference causes an
access exception, the exception is indicated. The
information provided for control register positions
not associated with an installed facility is unpredicta­
ble.
The second operand must be designated on a
word boundary; otherwise, a specification exception
is recognized, and the operation is suppressed.
Condition Code: The code remains unchanged.
Program Exceptions:
Privileged operation
Access (store, operand 2)
Specification
Programmiing Note
Although on some CPUs STORE CONTROL may
provide zeros in the bit positions corresponding to
the unassigned register positions, the program should
not depend on such zeros.
Store CPU Address
STAP [S]
[ __ B_2_1_2 ______ __ _____ D_2 __ o 16 20 31
The processor address by which this CPU is identi­
fied in a multiprocessing system is stored at the half­
word location designated by the second-operand
address.
The operand must be designated on a halfword
boundary; otherwise, a specifIcation exception is
recognized, and the operation is suppressed. The
operation :is suppressed on protection and. addressing
exceptions.
Condition Code: The code remains unchanged.
Program Exceptions: Operation (if the multiprocessing feature is no; installed)
Privileged operation
Access (store; operand 2)
Specification
112 System/370 Principles of Operation
Store CPU ID
STIDP [S] B202 o 16 20 Information identifying the CPU is stored at the
doubleword location designated by the second­
operand address.
The format of the information is as follows:
Version Code CPU Identification Number
o 8
31
31 Model Number Maximum MeEL Length I 32 48 63
The version-code field, bit positions 0-7, contains
model-dependent information, not otherwise easily
obtained, that is normally of importance only in
model-dependent recovery or diagnostic programs.
Bit positions 8-31 contain the CPU identification
number, consisting of six digits: a high-order zero
digit and five digits selected from the physical serial
number stamped on the CPU, or six digits selected
from the serial number. The contents of the CPU identification-number field, in conjunction with the
model number, permit unique identification of the CPU. Bit positions 32-47 contain the model number,
consisting of four digits: a high-order zero digit and
the three digits of the model number, such as 0145 or 0168. Bit positions 48-63 contairt a 16-bit binary value
indicating the length in bytes of the longest machine­
check extended logout (MCEL) that can be stored
by the CPU. The operand must be designated on a dotibleword
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. The
operation is suppressed on protection and addressing
exceptions.
Condition Code: The code remains unchanged.
Program Exceptions:
Privileged operation . Access (store, operand 2)
Specification

Programming Notes
The program should allow for the possibility that the CPU identification number may contain the digits
A-F as well as the digits 0-9. The principal uses of the information stored by
the instruction STORE CPU ID are the following:
1. The CPU identification number, combined with
the model number, provides a unique CPU identification that can be used in associating
results with an individual system, particularly
in regard to functional differences, perform­
ance differences, and error handling.
2. The model number, in conjunction with the
version code, can be used by model­
independent programs in determining which
model-dependent recovery programs should be
called.
3. The MCEL length can be used by model­
independent programs to allocate main storage
for the MCEL area.
Store CPU Timer
[S] 8209 o 16 20 The current value of the CPU timer is stored at the
double word designated by the second-operand ad­
dress.
31
Zeros are provided for the rightmost bit positions
that are not updated by the CPU timer.
The operand must be designated on a doubleword
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. The
operation is suppressed on protection and addressing
exceptions.
Condition Code: The code remains unchanged.
Program Exceptions:
Operation (if the CPU timer is not installed)
Privileged operation
Access (store, operand 2)
Specification
Store Prefix
[S]
8211
o 16 20 31
The contents of the prefix register are stored at the
word location designated by the second-operand
address. Zeros are provided for bit positions 0-7 and 20-31. The operand must be designated on a word
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. The
operation is suppressed on protection and addressing
exceptions.
Condition Code: The code remains unchanged. Program Exceptions:
Operation (if the multiprocessing feature is not
installed)
Privileged operation
Access (store, operand 2)
Specification
Store Then AND System Mask
[SI]
AC 12 8,
o 8 16 20 D, 31
Bits 0-7 of the current PSW are stored at the first­
operand location. Then the contents of bit positions 0- 7 of the current PSW are replaced by the logical
product (AND) of their original contents and the
second operand.
The operation is suppressed on protection and
addressing exceptions.
Condition Code: The code remains unchanged. Program Exceptions:
Operation (if the translation feature is not in­
stalled)
Privileged operation
Programming Note
The STORE THEN AND SYSTEM MASK instruc­
tion permits the program to turn off selected bits in
the system mask while retaining the original contents
for later restoration. For example, in EC mode it
System-Control Instructions 113