The sign of the product is determined by the rules
of algebra from the multiplier and multiplicand sign,
except that a zero result is always positive.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2)
Programming Note
The significant part of the product usually occupies
46 bits or fewer, the exception being 47 bits when
both operands are maximum negative. Since the
low-order 32 bits of the product are stored un­
changed, ignoring all bits to the left, the sign bit of
the result may differ from the true sign of the prod­
uct in the case of overflow. OR OR Rl,R2 [RR]
16 I R, I R2 I 0 8 12 15 0 Rl,D2(X2,B2) [RX]
56 I R, I X
2 I 8
2 D2 0 8 12 16 20 31 01 Dl (Bl),h [81]
96 8
1
o 8 16 20 31
D6 I L
o 8
The OR of the first and second operands is placed in
the first-operand location. Operands are treated as unstructured logical
quantities, and the connective OR is applied bit by
bit. A bit position in the result is set to one if the
corresponding bit position in one or both operands
contains a one; otherwise, the result bit is set to
zero.
For OC, each operand field is processed left to
right. When the operands overlap, the result is ob-
tained as if the operands were processed one byte at
a time and each result byte were stored immediately
after the operand byte is fetched.
Resulting Condition Code:
o Result is zero
1 Result not zero
2 -
3 -
Program Exceptions:
Access (fetch, operand 2,0 and OC; fetch and
store, operand 1, 01 and OC) Programming Note
The instruction OR may be used to set a bit to one.
The execution of 01 and OC consists in fetching a
first-operand byte from main storage and subse­
quently storing the updated value. These fetch and
store accesses to a particular byte do not necessarily
occur one immediately after the other. Thus, the
instruction OR cannot be safely used to update a
shared location in main storage if the possibility ex­
ists that another CPU may also be updating the loca­
tion. For 01, only one byte is stored.
Pack
PACK [88] I 36 47 I o
F2
The format of the second operand is changed from
zoned to packed, and the result is placed in the first­
operand location.
The second operand is assumed to have the zoned
format. All zones are ignored, except the zone over
the low-order digit, which is assumed to represent a
sign. The sign is placed in the right four bits of the
low-order byte, and the digits are placed adjacent to
the sign and to each other in the remainder of the
result field. The sign and digits are moved un­
changed to the first operand field and are not
checked for valid codes.
The result is obtained as if the fields were pro­
cessed right to left. If necessary, the second operand
is extended with high-order zeros. If the first­
operand field is too short to contain all significant
digits of the second-operand field, the remaining
high-order digits are ignored.
General Instructions 13 7
When the operands overlap, the result is obtained
as if each result byte were stored immediately after
the necessary operand bytes are fetched. Two
second-operand bytes are needed for each result byte, except for the rightmost byte of the result
field, which requires only the rightmost second­
operand byte.
Condition Code:
The code remains unchanged. Program Exceptions:
Access (fetch, operand 2; store, operand 1)
Programming Notes
The PACK instruction may be used to interchange
the two hex digits in one byte by specifying a zero in
the Lt and L2 fields and the same address for both
operands.
To remove the zones of all bytes of a field, in­
cluding the low-order byte, both operands must be
extended with a dummy byte in the low-order posi­
tion, which subsequently is ignored in the result
field.
Set Program Mask SPM Rt [RR]
Bits 2-7 of the general register specified by the R t
field repllace the condition code and the program
mask bits of the current PSW. Bits 12-15 of the in­
struction are ignored.
Bits 0, 1, and 8-31 of the register specified by the
Rt field are ignored. The contents of the register
specified by the Rt field remain unchanged.
The instruction permits setting of the condition
code andl the mask bits in either the problem or su­
pervisor state. Conditim' Code:
The code is set according to bits 2 and 3 of the
register specified by Rt.
Program Exceptions:
None
Programming Note
Bits 2-7 of the general register may have been load­
ed from the PSW by BRANCH AND LINK.
138 System/370 Principles of Operation
Shift Left Double
SLDA [RS]
o 8 12 16 20 31
The double-length integer part of the first operand is
shifted left the number of bits specified by the
second-operand address. Bits 12-15 of the instruc­
tion are ignored.
The Rt field of the instruction specifies an even­
odd pair of registers and must designate an even­
numbered register. When Rt is odd, a specification
exception is recognized.
The second-operand address is not used to ad­
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
The first operand is treated as a number with 63
integer bits and a sign in the sign position of the
even register. The sign remains unchanged. The
high-order position of the odd register contains an
integer bit, and the contents of the odd register par­
ticipate in the shift in the same manner as the other
integer bits. Zeros are supplied to the vacated posi­
tions of the registers.
If a bit unlike the sign bit is shifted out of bit posi­
tion 1 of the even register, an overflow occurs. The
overflow causes a program interruption when the
fixed-point overflow mask bit is one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow Program Exceptions:
Specification
Fixed-Point Overflow Programming Notes
The eight shift instructions provide the following
three pairs of alternatives: left or right, single or
double, and algebraic or logical. The algebraic shifts
differ from the logical shifts in that, in the algebraic
shifts, overflow is recognized, the condition code is
set, and the high-order bit participates as a sign.
The maximum shift amount which can be speci­
fied is 63. For algebraic shifts this is sufficient to
shift out the entire integer field. Since 64 bits partici­
pate in the double-logical shifts, the entire register
contents cannot be shifted out.
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