performance, of the physical construction and the
use of distinct storage media are not observable by
the program.
Fetching and storing of data by the CPU are not
affected by any concurrent 110 data transfer or by
concurrent reference to the same storage location by
another CPU. When concurrent requests to a main­
storage location occur, access normally is granted in
a sequence that assigns highest priority to references
by channels and that alternates priority between CPUs. If the first reference changes the contents of
the location, any subsequent storage fetches obtain
the new contents.
Main storage may be volatile or nonvolatile. If it
is volatile., the contents of main storage are not pre­
served when power is turned off. If it is nonvolatile,
turning power off or on does not affect the contents
of main storage, provided the CPU is in the stopped
state and no references are made to main storage by
channels when power is turned off. In both types of
main storage, the contents of the keys in storage
associated with protection are not necessarily pre­
served when the power for main storage is turned
off. Informcltion Formats
The system transmits information between main
storage and a CPU or channel in units of eight bits,
or a multiple of eight bits, at a time. Each eight-bit
unit of information is called a byte, the basic building
block of all formats.
The bits in a byte are numbered consecutively,
left to right, 0 through 7. Within any program format
or any fixed-length operand format of multiple
bytes, the bits making up the format are consecu­
tively numbered from left to right, starting with the
number O. Leftmost bits are sometimes referred to as
the "high-order" bits and rightmost bits as the "low­
order" bits.
For purposes of error detection, and in some
models for correction, one or more check bits are
transmitted with each byte or with a group of bytes.
The check bits are generated automatically by the
system and cannot be directly controlled by the pro­
gram. References in this manual to the size of data
fields and registers exclude mention of the associated
check bits. All storage capacities are expressed in
number of bytes provided, without regard to storage
width.
Bytes may be handled separately or grouped to­
gether in fields. A hal/word is a group of two con­
secutive bytes and is the basic building block of in­
structions .. A word is a group of four consecutive
bytes; a doubleword is a group of eight bytes. The
14 System/370 Principles of Operation
location of any field or group of bytes is specified by
the address of its leftmost byte.
The length of fields is either implied by the opera­
tion to be performed or stated explicitly as part of
the instruction. When the length is implied, the in­
formation is said to have a fixed length, which can
be either one, two, four, or eight bytes.
When the length of a field is not implied by the
operation code, but is stated explicitly, the informa­
tion is said to have variable field length. Variable­
length operands are variable in length by increments
of one byte.
When information is placed in main storage, the
contents of only those byte locations are replaced
that are included in the designated field, even though
the width of the physical path may be wider than the
field being stored.
Addressing
Byte locations in storage are consecutively num­
bered, left to right, starting with 0; each number is
considered the address of the corresponding byte. A
group of bytes in storage is addressed by the left­
most byte of the group. The number of bytes in the
group is either implied or explicitly defined by the
operation. The addressing arrangement uses a 24-bit
binary address to accommodate a maximum of
16,777,216 byte addresses.
Storage addressing wraps around from the maxi­
mum byte address, 16,777,215, to address o. In­
formation may be located partially in the last and
partially in the first location of storage and is proc­
essed without any special indication of crossing the
maximum address boundary.
For purposes of addressing main storage, three
types of addresses are recognized: absolute, real, and
logical.
Absolute addresses are the lowest level of
program-recognizable addresses, and in this manual
they are considered to be the addresses of actual
storage locations. On some models, storage­
configuration controls may be provided which permit
the operator to change the correspondence between
absolute addresses and the actual physical storage
locations. However, at anyone time, a physical stor­
age location is not associated with more than one
absolute address.
When the multiprocessing feature is included in a CPU, an address reassignment mechanism is provid­
ed that permits the first 4,096 bytes of real main
storage for each CPU to be assigned to different
absolute storage locations. This reassignment mecha­
nism is called "prefixing." Most addresses generated
in the CPU are monitored by the prefixing mecha­
nism and reassigned when necessary. Addresses sub-

ject to monitoring by the prefixing mechanism are
referred to as "real" addresses. When prefixing is
not installed, a real address and the corresponding
absolute address are identical.
When dynamic address translation is invoked,
addresses specified by the program are normally
translated to real addresses before main storage is
accessed. The address specified by the program is
referred to as a logical address. When dynamic ad­
dress translation is not invoked, a logical address and
the corresponding real address are identical.
All CPUs and channels having access to a com­
mon main-storage location have access to the entire 2,048-byte block containing that location and the
associated key in storage. All CPU s and channels
refer to a shared main-storage location by using the
same absolute address.
Available storage is normally assigned to contigu­
ous absolute addresses starting at address 0, and is
always assigned in multiples of 2,048 bytes. An ex­
ception condition is recognized when an attempt is
made to access main storage by using an absolute
address that does not correspond to a tion. Normally, the exception condition is recognized
only when the information associated with the abso­
lute address is actually required and not when the
operation can be completed without using the in­
formation.
In/ormation Positioning
Integral Boundaries
Certain units of information must be located in main
storage on an integral boundary. A boundary is
called integral for a unit of information when its
storage address is a mUltiple of the length of the unit
in bytes. For example, a word (four bytes) is on an
integral boundary when it is located in storage so
that its address is a multiple of the number 4. A half­
word (two bytes) is on an integral boundary when it
has an address that is a multiple of the number 2,
and a doubleword (eight bytes) is on an integral
boundary when it has an address that is a mUltiple of
the number 8.
When storage addresses designate half words,
words, and doublewords on integral boundaries, the
binary representation of the address contains one,
two, or three low-order zero bits, respectively.
Instructions must appear on halfword integral
boundaries, and channel command words and the
operands of certain privileged instructions must ap­
pear on integral boundaries. • t + I I I bf!f Jk + I I I kf;:!'! ; f Integral Boundaries for Halfwords, Words, and Doublewords
Byte-Oriented-Operand Feature
The byte-oriented-operand feature is standard on
System/370. This feature permits storage operands
of most unprivileged operations to appear on any
byte boundary.
The feature does not pertain to instruction ad­
dresses, or to the operands for COMPARE AND SWAP (CS) and COMPARE DOUBLE AND SW AP (CDS). Instructions must appear on even
byte boundaries. The low-order bit of a branch ad­
dress must be zero, and the instruction EXECUTE
must designate the subject instruction at an even
byte address. COMP ARE AND SWAP must desig­
nate a word boundary, and COMPARE DOUBLE AND SW AP must designate a doubleword bounda­
ry. Significant performance degradation is possible
when storage operands are not positioned at ad­
dresses that are integral multiples of the operand
length. To ensure optimum performance, storage
operands should be aligned on integral boundaries,
and the use of unaligned operands should be re­
served for exceptional cases.
Central Processing Unit The central processing unit (CPU) is the controlling
center of the system. It contains the sequencing and
processing controls for instruction execution, inter­
ruption action, timing facilities, initial program load- System Organization 15