Shift amounts from 31-63 cause the entire integer
to be spifted out of the register. When the entire
integer field of a positive number has been shifted­ out, the register contains a value of zero. For a nega­
tive number, the register contains a value of -1.
Shift Right Single Logical
SRL Rt,D2(B2) [RS]
88 R, 1883 B2 I o 8 12 16 20 The first operand is shifted right the number of bits
specified by the second-operand address. Bits 12-15
of the instruction are ignored.
The second-operand address is not used to ad-
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
All 32 bits of the first operand participate in the
shift. Low-order bits are shifted out without inspec­
tion and are lost. Zeros are supplied to the vacated
high-order register positions.
Condition Code:
The code remains unchanged.
Program Exceptions:
None
Store
ST [RX] 50 o 8 12 16 20 The first operand is stored at the seGond-operand
location.
31
The 32 bits in the general register are placed un­
changed at the second-operand location.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (store, operand 2)
Store Character
STC [RX]
42
o 8 12 16 20 31
The contents of bit positions 24-31 of the general
register designated by the Rt field are placed un­
changed at the second-operand location. The second
operand is one byte in length.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (store, operand 2)
Store Characters Under Mask
BE R, I M3 I B2 D2
o 8 12 16 20 31
Bytes selected from the first operand under control
of a mask are placed in contiguous byte locations
beginning at the second-operand address.
The contents of the M3 field, bit positions 12-15,
are used as a mask. The four bits of the mask, left to
right, correspond one for one with the four bytes,
left to right, of the general register designated by the
R t field. The bytes corresponding to ones in the
mask are placed in the same order in successive and
contiguous storage locations beginning with the loca­
tion designated by the second-operand address. The
number of bytes stored is equal to the number of
ones in the mask. The contents of the general regis­
ter remain unchanged.
When the mask is not zero, exceptions associated
with storage-operand access are recognized only for
the number of bytes specified by the mask. When
the mask is zero, no access exceptions are recognized.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (store, operand 2)
Store Clock
STCK [S] 8205 o 16 20 31
The current value of the time-of-day clock is stored
at the eight-byte field designated by the second-
General Instructions 141

operand address, provided the clock is in the: set,
stopped, or not-set state.
The value of the clock is expressed as an un­
signed, 64-bit fixed-point number. Zeros are stored
for the low-order bit positions that are not provided
by the clock.
When the clock is in the error state, the value
stored is unpredictable. When the clock is in the
not-operational state, zeros are stored at the oper­
and location. The quality of the clock value stored by the in­
struction is indicated by the resultant code
setting.
A serialization function is performed before the
value of the clock is fetched and again after the val­
ue is placed in main storage. CPU operation is de­
layed until all previous accesses by this CPU to main
storage have been completed, as observed by chan­
nels and other CPUs, and then the value of the clock
is No subsequent instructions or their oper­
ands are fetched by this CPU until the clock value
has been placed in main storage, as observcd by
channels and CPUs. Condition Code:
o Clock in set state
1 Clock in not-set state
2 Clock in error state
3 Clock in stopped state or not-operational state
Program Exceptions:
Access (store, operand 2)
Programming Notes
Condition code 0 normally indicates that the clock
has been set by the control program. Accordingly,
the value may be used in elapsed-time measurements
and as a valid time-of -day and calendar indication.
Condition code 1 indicates that the clock's value is
the elapsed time since the power for the cloek was
turned on. In this case the value may be used in
elapsed time measurements but is not a valid time­
of -day indication. Condition codes 2 and 3 mean
that the value provided by STORE CLOCK cannot
be used for time measurement or indication.
Condition code 3 indicates that the clock is either
in the stopped state or not-operational state .. These
two states can normally be distinguished since an
all-zero value is stored when in the not-operational
state.
Bit position 31 of the clock is incremented every
1.048576 seconds; hence, for timing applications involving human responses, the high-order clock
word may provide sufficient resolution.
142 System/370 Principles of Operation To provide compatible operation from one system
to another requires the establishment of a standard
time origin, or epoch, that is, the calendar date and
time to which a clock value of zero corresponds.
January 1, 1900,0 A.M. Greenwich Mean Time is
recommended as the standard epoch for the clock,
although some early support of the TOD clock is not
based on this epoch. A program using the clock's
value as a time-of-day and calendar indication may
have to be aware of the support under which it is
running. With the standard epoch, bit 0 of the TOD clock turns on May 11, 1971 at 11:56:53.685248
A.M. GMT. Therefore, in most cases, the program
can test the high-order bit to determine if the TOD clock value is the standard epoch.
Because of the inaccuracies in setting the clock
value on the basis of a synchronization signal pro­
vided by the operator, the low-order bit positions of
the clock, expressing fractions of seconds, normally
are not valid as indications of time of day. However,
they permit elapsed time measurements of high reso­
lution.
Store Hal/word STH [RX] 40 R1
o 8 12 16 20 31
The contents of bit positions 16-31 of the general
register designated by the Rl field are placed un­
changed at the second-operand location. The second
operand is two bytes in length.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (store, operand 2)
Store Multiple STM [RS] 90 o 8 12 16 20 31
The set of general registers starting with the register
specified by Rl and ending with the register speci­
fied by R3 is stored at the locations designated by
the second-operand address.