Programming Notes
With short and long operands, the halve operation is
identical to a divide operation with the number 2 as
divisor. Similarly, the result of HDR is identical to
that of MD or MDR with one-half as a multiplier.
No multiply operation corresponds to HER, since no
multiply operation produces short results.
The result of HALVE is replaced by a true zero
only when the second-operand fraction is zero, or
when exponent underflow occurs with the exponent­
underflow mask set to zero. When the fraction of the
second operand is zero, except for the low-order bit
position, the low-order one is shifted into the guard
digit position and participates in the postnormaliza­
tion.
Load
LER Rl,R2
[RR, Short Operands]
38
o 8 12 15
LE Rl,D2(X2,B2)
[RX, Short Operands]
78 I R, I X21 8
2 I D2 I 0 8 12 16 20 31
LDR Rl,R2
[RR, Long Operands]
28 I R, I R2 I 0 8 12 15
LD R 1 ,D2(X2,B2)
[RX, Long Operands] I 68 I R,I x 2 I 8
2 D2 0 8 12 16 20 31
The second operand is placed unchanged in the first­
operand location.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
Condition Code:
The code remains unchanged.
Program Exceptions:
Operation (if the floating-point feature is not
installed)
Access (fetch, operand 2 of LE and LD only)
Specification
Load and Test
LTER Rl,R2
[RR, Short Operands]
o 8 12 15
LTDR R 1,R2
[RR, Long Operands]
22
o 8 12 15
The second operand is placed unchanged in the first­
operand location, and its sign and magnitude are
tested to determine the setting of the condition code.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception isrecog­
nized.
ResUlting Condition Code: ° Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions:
Operation (if the floating-point feature is not
installed)
Specification
Programming Note
When the same register is specified as the first­
operand and second-operand location, the operation
is equivalent to a test without data movement.
Load Complement
LeER R 1,R2
[RR, Short Operands]
33
o 8 12 15
Floating-Point Instructions 165
LCDR Rl,R2
[RR, Long Operands] The second operand is placed in the first-operand
location with the sign changed to the opposite value.
The sign bit is inverted, even if the fraction is
zero. The eharacteristic and fraction are not
changed.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
Resulting Condition Code: ° Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions: Operation (if the floating-point feature is not
installed)
Specification
Load Negative
LNER Rl,R2
[RR, Short Operands] LNDR Rl,R2
[RR, Long Operands] o 8 12 15
The second operand is placed in the first-operand
location with the sign made minus.
The sign bit is made one, even if the fraction is
zero. The characteristic and fraction are not
changed.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
166 System/370 Principles of Operation Resulting Condition Code: ° Result fraction is zero
1 Result is less than zero
2 -
3 -
Program Exceptions: Operation (if the floating-point feature is not
installed)
Specification
Load Positive LPER Rl,R2
[RR, Short Operands] 30 o 8 12 15 LPDR Rl,R2
[RR, Long Operands] 20 o 8 12 15
The second operand is placed in the first-operand
location with the sign made plus.
The sign bit is made zero. The characteristic and
fraction are not changed.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
Resulting Condition Code: ° Result fraction is zero
1 -
2 Result is greater than zero
3 -
Program Exceptions:
J Operation (if the floating-point feature is not
installed)
Specification
Load Rounded
LRER Rl,R2
[RR, Long Operand 2, Short Operand 1]
35
o 8 12 15
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