Multiplication of two floating-point numbers con­
sists in exponent addition and fraction multiplica­
tion. The operands are prenormalized, and the sum of the characteristics of the normalized operands,
less 64, is used as the characteristic of the intermedi­
ate product.
The product of the fractions is developed such
that the result has the exact fraction product truncat­
ed to the proper result-fraction length. When the
result is normalized without requiring any postnor­
malization, the intermediate-product fraction is trun­
cated to the result-fraction length, and the
intermediate-product characteristic becomes the
final product characteristic. When the intermediate­
product fraction has one leading zero digit, it is shift­
ed left one digit position, bringing the contents of
the guard-digit position into the low-order position
of the result fraction, and the intermediate-product
characteristic is reduced by one. The intermediate­
product fraction is subsequently truncated to the
result-fraction length.
For MER and ME, the multiplier and multipli­
cand have six-digit fractions, and the product frac­
tion has the full 14 digits of the long format, with the
two low-order fraction digits always zero. For MDR
and MD, the multiplier and multiplicand fractions
have 14 digits, and the result product fraction is
truncated to 14 digits. For MXDR and MXD, the
multiplier and multiplicand fractions have 14 digits,
with the multiplicand occupying the high-order part
of the first operand; the result product fraction con­
tains 28 digits and is an exact product of the operand
fractions. For MXR, the multiplier and multiplicand
fractions have 28 digits, and the result product frac­
tion is truncated to 28 digits.
The sign of the product is determined by the rules
of algebra, unless all digits of the product fraction
are zero, in which case the sign is made plus.
An exponent-overflow exception is recognized
when the characteristic of the normalized product
exceeds 127 and the fraction of the product is not
zero. The operation is completed by making the
characteristic 128 less than the correct value. If, for
extended results, the low-order characteristic also
exceeds 127, it, too, is decreased by 128. The result
is normalized, and the sign and fraction remain cor­
rect. A program interruption for exponent overflow
then occurs.
Exponent overflow is not recognized if the
intermediate-product characteristic exceeds 127 but
is brought within range by normalization.
An exponent-underflow exception exists when the
characteristic of the normalized product is less than
zero and the fraction of the product is not zero. If
the exponent-underflow mask bit is one, the opera-
168 System/370 Principles of Operation
tion is completed by making the characteristic 128
larger than the correct value, and a program inter­
ruption for exponent underflow occurs. The result is
normalized, and the sign and fraction remain correct.
If the exponent-underflow mask bit is zero, program
interruption does not take place; instead, the opera­
tion is completed by making the product a true zero.
For extended results, exponent underflow is not
recognized when the low-order characteristic is less
than zero but the high-order characteristic is zero or
above.
Exponent underflow is not recognized when the
characteristic of an operand becomes less than zero
during pre normalization, but the characteristic of the
normalized product is within range.
When either or both operand fractions are zero,
the result is made a true zero, and no exceptions are
recognized.
The Rl field for MER, ME, MDR, and MD, and
the R2 field for MER, MDR, and MXDR must des­
ignate register 0, 2, 4, or 6. The Rl field for MXDR,
MXD, and MXR, and the R2 field for MXR must
designate register 0 or 4. Otherwise, a specification
exception is recognized.
Com/ition Code:
The code remains unchanged.
Program Exceptions: Operation (if the floating-point feature is not
installed, or, for MXDR, MXD, and MXR, if
the extended-precision floating-point feature is
not installed)
Access (fetch, operand 2 of ME, MD, and MXD
only)
Specification
Exponent Overflow Exponent Underflow Progranrurndng Interchanging the two operands in a floating-point
multiplication does not affect the value of the prod­
uct.
Store STE Rl,D2(X2,B2)
[RX, Short Operands] 70 o 8 12 16 20 31

STD Rl,D2(X2,B2)
[RX, Long Operands] 60 o 8 12 16 20 31
The first operand is placed unchanged at the second­
operand location.
The Rl field must designate register 0, 2, 4, or 6;
otherwise, a specification exception is recognized.
Condition Code:
The code remains unchanged.
Program Exceptions: Operation (if the floating-point feature is not
installed)
Access (store, operand 2)
Specification
Subtract Normalized
SER Rl,R2
[RR, Short Operands] 38
o 8 12 15
SE Rl,D2(X2,B2)
[RX, Short Operands] SDR Rl,R2
[RR, Long Operands] 28
o 8 12 15
SD R 1 ,D2(X2,B2)
[RX, Long Operands] 68
o 8 12 16 20 31
SXR Rl,R2
[RR, Extended Operands] 37
o
The second operand is subtracted from the first OPer­ and, and the normalized difference is placed in the
first-operand location.
The execution of SUBTRACT NORMALIZED is
identical to that of ADD NORMALIZED, except
that the second operand participates in the operation
with its sign bit inverted.
The Rl field of SER, SE, SDR, and SO, and the
R2 field of SER and SDR must designate register 0, 2,4, or 6. The Rl and R2 fields of SXR must desig­
nate register 0 or 4. Otherwise, a specification excep­
tion is recognized.
Resulting Condition Code:
o Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions: Operation (if the floating-point feature is not
installed, or, for SXR, if the extended-precision
floating-point feature is not installed)
Access (fetch, operand 2 of SE and SO only)
Specification
Exponent Overflow Exponent Underflow Significance
Subtract Unnormalized SUR Rl,R2
[RR, Short Operands J
3F I R, I :J o 8 12 15 SU Rl,D2(X2,B2)
[RX, Short Operands j L- ___ 7_F ____ __ __ _____ o 8 12 16 20 31 Floating-Point Instructions 169