STD Rl,D2(X2,B2)
[RX, Long Operands] 60 o 8 12 16 20 31
The first operand is placed unchanged at the second­
operand location.
The Rl field must designate register 0, 2, 4, or 6;
otherwise, a specification exception is recognized.
Condition Code:
The code remains unchanged.
Program Exceptions: Operation (if the floating-point feature is not
installed)
Access (store, operand 2)
Specification
Subtract Normalized
SER Rl,R2
[RR, Short Operands] 38
o 8 12 15
SE Rl,D2(X2,B2)
[RX, Short Operands] SDR Rl,R2
[RR, Long Operands] 28
o 8 12 15
SD R 1 ,D2(X2,B2)
[RX, Long Operands] 68
o 8 12 16 20 31
SXR Rl,R2
[RR, Extended Operands] 37
o
The second operand is subtracted from the first OPer­ and, and the normalized difference is placed in the
first-operand location.
The execution of SUBTRACT NORMALIZED is
identical to that of ADD NORMALIZED, except
that the second operand participates in the operation
with its sign bit inverted.
The Rl field of SER, SE, SDR, and SO, and the
R2 field of SER and SDR must designate register 0, 2,4, or 6. The Rl and R2 fields of SXR must desig­
nate register 0 or 4. Otherwise, a specification excep­
tion is recognized.
Resulting Condition Code:
o Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions: Operation (if the floating-point feature is not
installed, or, for SXR, if the extended-precision
floating-point feature is not installed)
Access (fetch, operand 2 of SE and SO only)
Specification
Exponent Overflow Exponent Underflow Significance
Subtract Unnormalized SUR Rl,R2
[RR, Short Operands J
3F I R, I :J o 8 12 15 SU Rl,D2(X2,B2)
[RX, Short Operands j L- ___ 7_F ____ __ __ _____ o 8 12 16 20 31 Floating-Point Instructions 169

SWR Rl,R2
[RR, Long Operands] o 8 12 15
SW Rl,D2(X2,B2)
[RX, Long Operands] o 8 12 16 20 31
The second operand is subtracted from the first oper­
and, and the unnormalized difference is placed in
the first··operand location.
The execution of SUBTRACT UNNORNlAL­ IZED is identical to that of ADD UNNORMAL- 170 System/370 Principles of Operation IZED, except that the second operand participates in
the operation with its sign bit inverted.
The Rl and R2 fields must designate register 0, 2,
4, or otherwise,. a specification exception is recog­
nized.
Resulting Condition Code: ° Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 - Program Exceptions: Operation (if the floating-point feature is not
installed)
Access (fetch, operand 2 of SU and SW only)
Specification
Significance