Type of IReference Set Storage Key I nsert Storage Key
Reset Reference Bit
Fetch, Nonzero Protection Key
Store, Nonzero Protection Key
Fetch, Ze'ro Protection Key
Store, Zem Protection Key
Explanation:
For Protection Bits Complete; validate. PO; preserve. PO or complete;
preserve. MC; preserve. MC 1
; preserve.
Complete; preserve.
Complete; preserve.
Action Taken on Invalid CBC For Reference and Change Bits
Complete; validate. PO in EC mode, PO or
complete in BC mode;
preserve. PO; preserve. MC or complete;
preserve. MC or complete;
preserve or correct. Complete; preserve.
Complete; preserve or
correct.
For Protection Bits and
Reference and Change Bits
Complete; validate. PO; preserve. PO; preserve. MC; preserve.
Me
1
; preserve. Complete; preserve.
Complete; preserve
2
.
Complete The condition does not cause termination of the execution of the instruction and, unless an unrelated
condition prohibits it, the execution of the instruction is completed, ignoring the error condition.
No machine-check damage conditions are generated, but recovery-report conditions may be generated. PO A machine-check instruction processing damage or system damage condition is recognized. MC Same as PO for CPU references, but an I/O reference may result in the following combinations of I/O interruption and machine-check interruption.
a) Channel control check and no machine-check interruption.
Validate
b) Channel control check and a recovery report.
cl External damage and no I/O interruption.
d) System damage and no I/O interruption.
The entire key is set to the new value with valid CBC. Preserve The contents of the entire checking block having invalid CBC are left unchanged. Correct The reference and change bits are set to one with valid CBC. The contents of the main-storage location are not changed.
2 On models with separate checking blocks for protection bits and for change and reference bits; the protection
bits are preserved, and the change and reference bits may be corrected or preserved.
Handling of Invalid CBC in Keys in Storage word boundary, and LOAD HALFWORD (LH)
validates if the operand is on a half word boundary.
Floating-point registers are validated by LOAD (LDR) and, if the operand is on a double word
boundary, by LOAD (LD).
Control registers may be validated either singly or
in groups by using the instruction LOAD CONĀ­ TROL (LCTL).
The CPU timer and clock comparator arc validatĀ­
ed by SET CPU TIMER (SPT) and SET CLOCK COMPARATOR (SCKC), respectively.
The TOD clock is validated by SET CLOCK (SCK) if the TOD clock security switch is in the
enable-set position.
174 System/370 Principles of Operation Programming Note
To provide for a model-independent machine-check
first-level-interruption handler, registers must be
validated before they are used. Examples: START I/O, SET SYSTEM MASK, and SET CLOCK should not be executed until control register 0 (containing block-multiplexing control, SSMĀ­
suppression control, and TOD clock synchronization
control bits), is validated. MONITOR CALL should
not be issued until control register 8, containing the
monitor class masks, is validated. Extended channel
masks, external masks, and machine-check controls
should be validated before the associated interrupĀ­
tions are allowed. The clock comparator and CPU timer should be validated before clock-comparator
and CPU-timer interruptions are allowed.
Check-Stop State
In certain situations it is impossible or undesirable to
continue operation when a machine error occurs. In
these cases, the CPU may enter the check-stop state.
When the CPU is in the check-stop state, the
condition is indicated by an error indicator, an audiĀ­
ble signal, or both. The system indicator is off, but
the state of the manual indicator depends on the
model. The exact indication of check-stop state is
model-dependent and is described in the System Library (SL) publication for the CPU. The machine enters the check-stop, state only as a
result of exigent conditions. The machine may be
removed from the check-stop state by CPU reset.
When the CPU is in the check-stop state, instrucĀ­
tions and interruptions are not executed. The interĀ­
val timer is not updated, and channel operations may
be suspended. The TOD clock is not normally affectĀ­
ed by check-stop state. The CPU timer mayor may
not run-in check-stop state, depending on the error
and the model. The CPU cluster meter does not run,
and the clock-out and metering-out lines are down.
The stop key and start key are not operative during
this state.
In a multiprocessing system, a CPU entering the
check-stop state generates a request for a
malfunction-alert external interruption to all CPUs configured to this CPU. Machine-Check Interruption
Conditions
Equipment malfunctions and other conditions reĀ­
sponsible for machine-check interruptions are reĀ­
ferred to as machine-check interruption conditions.
Two major types of conditions are identified: exigent
conditions and repressible conditions.
Repressible Conditions
Repressible conditions are those in which the seĀ­
quential processing capability of the CPU has not
been affected. Repressible conditions can be delayed
until the completion of the current instruction, and
in most cases, even longer, without affecting the
integrity of the CPU operation. Repressible condiĀ­
tions are of three types: recovery, alert, and repress'Ā­
ible damage. Each has one or more subclasses as
follows:
A hardware malfunction successfully corrected or
circumvented without loss of system integrity is
called a recovery condition. Depending on the model
and the type of malfunction, some recovery condiĀ­
tions may be discarded and not reported. Recovery
conditions that are reported are grouped in one subĀ­
class, system recovery.
Page of GA22-70004 Revised September 1, 1975
By TNL: GN22-0498
A machine-check interruption condition not diĀ­
rectly related to a hardware malfunction is called an
alert condition. The alert conditions contain two
subclasses: degradation and warning.
A hardware malfunction resulting in the loss of
integrity of a process in .the system but not directly
affecting the sequential CPU operation is called a
repressible damage condition. Repressible damage
conditions are divided into three subclasses, identifyĀ­
ing the process affected: timer damage, timingĀ­
facility damage, and external damage.
Exigent Conditions
Exigent conditions are those in which direct damage
has occurred to the CPU operation, and the current
instruction or interruption cannot safely continue.
Exigent conditions are divided into two subclasses:
instruction-processing damage, and system damage.
Malfunctions which cannot be isolated to a specific
process are indicated as system damage.
Machine-Check Interruption
The machine-check interruption provides a means of
reporting equipment malfunction and certain exterĀ­
nal disturbances, and it supplies the program with
information about the extent of the resultant damage
and the location and nature of the cause.
Interruption Action
A machine-check interruption causes the PSW reĀ­
flecting the point of interruption to be stored as the
machine-check old PSW at location 48; extended
machine-check interruption information is stored,
consisting of the information in all the control regisĀ­
ters, general registers, floating-point registers, CPU timer, clock comparator, a region code, and a failing
storage address. Then the machine-check interrupĀ­
tion code (MCIC) of eight bytes is stored. A new PSW is fetched from location 112. Additionally,
sometime before the storing of the machine-check
interruption code, one or several machine-check
logouts may have occurred. The machine-generated
addresses to reference the old and new PSW, the
interruption code and extended interruption informaĀ­
tion, and the fixed logout area are all real addresses.
The extended machine-check logout address is also a
real address. If the machine-check interruption code
cannot be stored successfully or the new PSW canĀ­
not be fetChed successfully, the CPU enters the
check-stop state if the check-stop control bit is one.
A machine-check interruption due to a repressible
machine-check condition can occur only when both PSW bit 13 and the associated subclass mask are
ones. A repressible machine-check interruption does
not terminate the execution of the current instruc-
Machine-Check Handling 175
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