Type of IReference Set Storage Key I nsert Storage Key
Reset Reference Bit
Fetch,Nonzero Protection Key
Store, Nonzero Protection Key
Fetch, Ze'ro Protection Key
Store,Zem Protection Key
Explanation:
For Protection BitsComplete; validate. PO; preserve. PO or complete;
preserve.MC; preserve. MC 1
; preserve.
Complete; preserve.
Complete; preserve.
Action Taken onInvalid CBC For Reference and Change Bits
Complete; validate.PO in EC mode, PO or
complete inBC mode;
preserve.PO; preserve. MC or complete;
preserve.MC or complete;
preserve or correct.Complete; preserve.
Complete; preserve or
correct.
For Protection Bits and
Reference andChange Bits
Complete; validate.PO; preserve. PO; preserve. MC; preserve.
Me
1
; preserve.Complete; preserve.
Complete; preserve
2
.
Complete The condition does not cause termination of the execution of the instructionand, unless an unrelated
condition prohibitsit, the execution of the instruction is completed, ignoring the error condition.
No machine-check damage conditions are generated, but recovery-report conditions may be generated.PO A machine-check instruction processing damage or system damage condition is recognized. MC Same as PO for CPU references, but an I/O reference may result in the following combinations of I/O interruption and machine-check interruption.
a)Channel control check and no machine-check interruption.
Validate
b)Channel control check and a recovery report.
cl External damage and noI/O interruption.
d) System damage and noI/O interruption.
The entire key is set to the new value with validCBC. Preserve The contents of the entire checking block having invalid CBC are left unchanged. Correct The reference and change bits are set to one with valid CBC. The contents of the main-storage location are not changed.
2On models with separate checking blocks for protection bits and for change and reference bits; the protection
bits are preserved, and the change and reference bits may be corrected or preserved.
Handling of Invalid CBC in Keys inStorage word boundary, and LOAD HALFWORD (LH)
validates if the operand is on a half word boundary.
Floating-point registers are validated byLOAD (LDR) and, if the operand is on a double word
boundary, byLOAD (LD).
Control registers may be validated either singly or
in groups by using the instructionLOAD CONĀ TROL (LCTL).
TheCPU timer and clock comparator arc validatĀ
ed by SETCPU TIMER (SPT) and SET CLOCK COMPARATOR (SCKC), respectively.
TheTOD clock is validated by SET CLOCK (SCK) if the TOD clock security switch is in the
enable-set position.
174System/370 Principles of Operation Programming Note
To provide for a model-independent machine-check
first-level-interruption handler, registers must be
validated before they are used. Examples: STARTI/O, SET SYSTEM MASK, and SET CLOCK should not be executed until control register 0 (containing block-multiplexing control, SSMĀ
suppression control, andTOD clock synchronization
control bits), is validated.MONITOR CALL should
not be issued until control register 8, containing the
monitor class masks, is validated. Extended channel
masks, external masks, and machine-check controls
should be validated before the associated interrupĀ
tions are allowed. The clock comparator andCPU timer should be validated before clock-comparator
and CPU-timer interruptions are allowed.
Reset Reference Bit
Fetch,
Store, Nonzero Protection Key
Fetch, Ze'ro Protection Key
Store,
Explanation:
For Protection Bits
preserve.
; preserve.
Complete; preserve.
Complete; preserve.
Action Taken on
Complete; validate.
complete in
preserve.
preserve.
preserve or correct.
Complete; preserve or
correct.
For Protection Bits and
Reference and
Complete; validate.
Me
1
; preserve.
Complete; preserve
2
.
Complete The condition does not cause termination of the execution of the instruction
condition prohibits
No machine-check damage conditions are generated, but recovery-report conditions may be generated.
a)
Validate
b)
cl External damage and no
d) System damage and no
The entire key is set to the new value with valid
2
bits are preserved, and the change and reference bits may be corrected or preserved.
Handling of Invalid CBC in Keys in
validates if the operand is on a half word boundary.
Floating-point registers are validated by
boundary, by
Control registers may be validated either singly or
in groups by using the instruction
The
ed by SET
The
enable-set position.
174
To provide for a model-independent machine-check
first-level-interruption handler, registers must be
validated before they are used. Examples: START
suppression control, and
control bits), is validated.
not be issued until control register 8, containing the
monitor class masks, is validated. Extended channel
masks, external masks, and machine-check controls
should be validated before the associated interrupĀ
tions are allowed. The clock comparator and
and CPU-timer interruptions are allowed.