are detected on prefetched or unused data mayor
may not be reported, depending on the model. Storage Errol' (SE): Bit 16, when one,
indicates that a checking block in main storage con­
tains invalid CBC. Storage Errol' COn'ected (SC): Bit 17, when one,
indicates that a checking block in main storage con­
tained near·valid cac and that the data portion of
the information has been corrected before being
used by the CPU or channel. Depending on the
model, the contents of the checking block in main
storage mayor may not have been restored to valid
CBC. The presence and extent of the storage-error­
correction capability depends on the model.
Key in Storage /Jrror Uncorrected (KE): Bit 18,
when one, indicates that a key in storage contains
invalid eBC.
Programming Note
The storage·error-type bits do not in themselves
indicate the occurrence of damage because the error
detected may not have affected the result. The sub­
class bits indicate, in conjunction with the storage­
error-type bits, the area affected by the storage er­
ror. Interruption Code Validity Bits
Bits 20-31 <and bits 46 and 47 of the machine-check
interruption code are validity bits. Each bit indicates
the validity of a particular field in main storage.
With the exception of the storage logical validity bit
(bit 31), each bit is associated with a field stored
during the machine .. check interruption. When a va­
lidity bit is one, it indicates that this specific field is
valid with respect to the indicated point of interrup­
tion and that no error was detected when the data
was stored. When the bit is zero, one or more of the
following conditions may have occurred: the original
informatilon was incorrect, the original information
had invalid CSC, additional malfunctions were de­
tected during the s.toring of the information, or none
or only part of the information waS stored. Even
though the information is unpredictable, the machine
will attempt, when to ensure that the in­
formatioltl in storage has valid CBC and thus reduce
the possibility of additional machine checks being
caused. PSW EMWP Volldily (WP): Bit 20, when one,
indicates that bits 12-15 of the machine-check old PSW are correct. I HO System/370 Principles of Op.eration PSW Masks and Key Validity (MS): Bit 21, when
one, indicates that all PSW bits other than the inter­
ruption code, ILC, EMWP, instruction address, con­
dition code, and program mask of the machine-check
old PSW are correct. Program Mask and Condition Code Validity
(PM): Bit 22, when one, indicates that the program
mask and condition code in the machine-check old PSW are correct.
Imtruction Address Validity (1A): Bit 23, when one,
indicates that the instruction address in the old PSW is correct.
Failing-Storage Address Valid (FA): Bit 24, when
one, indicates that a correct failing-storage address
has been stored. The presence and extent of the
capability to indicate the failing-storage address de­
pend on the model. When no storage errors are re­
ported, that is, bits 16-18 of the machine-check in­
terruption code are zeros, the failing-storage address
is meaningless, even though it may be indicated as
valid.
Region Code Valid (RC): Bit 25, when one, indi­
cates that a correct region code has been stored. The
presence of the region code depends on the model.
Floating-Point Registers Valid (FP): Bit 27, when
one, indicates that the contents of the floating-point
register save area reflect the correct state of the
floating-point registers at the point of interruption.
When the floating-point feature is not installed, this
bit is set to zero.
General Registers Valid (GR): Bit 28, when one,
indicates that the contents stored in the general reg­
ister save area reflect the correct state of the general
registers at the point of interruption.
Control Registers Valid (CR): Bit 29, when one,
indicates that the contents stored in the control reg­
ister save area reflect the correct state of the control
registers at the point of interruption.
Logout Valid (LG): Bit 30, when one, indicates
that the CPU extended logout information was cor­
rectly stored. Storage Logical Validity (ST): Bit 31, when one,
indicates that the contents of those storage locations
which are modified by the instruction processing
stream contain the correct information relative to the
point of interruption. That is, all stores prior to the

point of interruption are completed, and all stores, if
any, beyond the point of interruption are suppressed.
When a store prior to the point of interruption is
suppressed because of an invalid CBC, the storage
logical validity bit may be indicated as one, provided
that the invalid CBC is preserved as invalid.
CPU Timer Valid: Bit 46, when one, indicates that
the CPU timer is not in error and that the contents
stored in the CPU-timer save area (location 216)
reflect the correct state of the CPU timer at the time
the interruption occurred.
Clock Comparator Valid: Bit 47, when one, indi­
cates that the clock comparator is not in error and
that the contents stored in the clock-comparator
save area (location 224) reflect the correct state of
the clock comparator.
Programming Note
The validity bits must be used in addition to the sub­
class indication and time-of -occurrence bits in order
to determine the extent of the damage caused by the
machine-check condition. The four PSW validity
bits, the three register validity bits, the two timing
facility validity bits, and the storage logical validity
bit must all be ones in addition to one of the follow­
ing in order to indicate that no damage has yet oc,­ curred to the system: • All of the damage subclass bits (0, 1,3,4,5)
are zeros. • Instruction processing damage is the only dam­
age subclass.bit which is one, the backed-up bit
is one, and the delayed bit is zero.
Machine-Check Extended Logout Length
Bits 48-63 of the machine-check interruption code
contain a 16-bit binary value indicating the length in
bytes of the information most recently stored in the
extended logout area, starting at the location speci-
fied by the machine-check extended logout pointer.
When no extended logout has occurred, this field is
set to zero.
Programming Note
When asynchronous machine-check extended log­
outs are permitted (control register 14, bit 8 is one),
more than one extended logout may have occurred.
The length stored on interruption does not necessari­
ly indicate the longest logout which has occurred.
Machine-Check Control Registers
Control Register 14
o 3
R DEW A
M M M M L
4 I : 10 Control register 14 contains mask bits that specify
whether certain conditions can cause machine-check
interruptions and control bits that determine when a
logout may occur. With the exception of bit 0, which
is provided on all models, each of the bits is neces­
sarily provided only if the associated function is pro­
vided.
Check-Stop Control
The check-stop control bit (CS), which is bit ° of
control register 14, controls the system action taken
when an exigent machine-check condition occurs
under one of the following two'conditions:
1. When the CPU is disabled for machine-check
interruptions (that is, PSW bit 13 is zero).
2. When a second exigent machine-check condi­
tion occurs during the process of storing the
machine-check interruption code, storing the machine-check old PSW, or fetching the
machine-check new PSW during a machine­
check interruption.
If the check-stop control bit is one and either
condition occurs, the machine the check-stop if the check-stop control bit is zeto, the ma­
chine may attempt to corttinue or may enter the
check-stop state, depending on the type of error and
the model. The check -stop control bit is initialized to
one. If damage occurs to control register 14, the
check-stop control bit is assumed to be one.
Logout Controls
Synchronous Machine-Check Extended Logout Con­
trol (SL): Bit 1 of control register 14 controls the
logout action during a machine-check interruption. If
the bit is one, the machine-check extended logout
area may be changed during the interruption; if the
bit is zero, the area may be chungedonly under con­
trol of the asynchronous machine-check extended
logout control bit (bit 8 of control register 14). Bit 1
of control register 14 is initialized to one.
Machine-Check l-landling 181