Program Execution
Contents Instructions .
Operands. Instruction Format
Register Operands I mmediate Operands
Storage Operands
Address Generation .
Program Status Word I nstruction Execution
Branching Interruptions. Sequence of Storage References I nstruction Fetch
DAT Table Fetches . Key-in·Storage Accesses
Storage-Operand References
Storage-Operand Fetch References
Storage-Operand Store References
Storage-Operand Update References
Storage-Operand Consistency . Single-Access References . Block-Concu rrent References
Consistency Specification . Relation Between Operand Accesses Serial ization .
Normally, operation of the CPU is controlled by
instructions taken in sequence. This sequence is
governed by the program status word (PSW), which
contains the primary information required for proper
program execution. A change in the sequential opera­
tion may be caused by branching, LOAD PSW, in­
terruptions, or manual intervention.
Instructions
Each instruction consists of two major parts: (1) an
operation code, which specifies the operation to be
performed, and (2) the designation of the operands
that participate. Operands Operands can be grouped in three classes: operands
located in registers, immediate operands, and oper­
ands in main storage. Operands may be either ex-
plicitly or implicitly designated.
Register operands can be located in general,
floating-point, or control registers, with the type of
register identified by the operation code. The regis­
ter containing the operand is specified by identifying
the register in a four-bit field, called the R field, in
the instruction. For some instructions an operand is · 19 · 19 ·20 ·20 ·20 ·20 · 21 ·22 .22
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located in an implicitly designated register, the regis­
ter being implied by the operation code.
Immediate operands are contained within the
instruction, and the eight-bit field containing the
immediate operand is called the I field.
Operands in main storage may either have an
implied length, be specified by a bit mask, or, in
other cases, be specified by a four-bit or eight-bit
length specification, called the L field, in the instruc­
tion. The addresses of operands in main storage are
specified by means of a format that uses the con­
tents of a general register as part of the address. This
makes it possible to: • Specify a complete address by using an abbrevi­
ated notation. • Perform address manipulation using instructions
which employ general registers for operands. • Modify addresses by program means without
alteration of the instruction stream. • Operate independently of the location of data
areas by directly using addresses received from
other programs.
The address used to refer to main storage either is
contained in a register designated by the R field in
the instruction or is calculated from a base address,
Program Execution 19

index, and displacement, designated by the B, X,
and D fields, respectively, in the instruction.
For purposes of describing the execution of in­
structions:, operands are designated as first and sec­
ond operands and, in some cases, third operal11ds.
In general, two operands participate in an instruc­
tion execlLltion, and the result replaces the first oper­
and. An exception is instructions with "store" in the
name, where the result replaces the second operand.
Except for storing the final result, the contents of all
registers and storage locations participating in the
addressing or execution part of an operation remain
unchanged. Instruction Format
An instruction is one, two, or three halfwords in
length and must be located in main storage on an
integral h:alfword boundary. Each instruction is in
one of six basic formats: RR, RX, RS, SI, S, and SS, with two variations of SS. Some instructions contain fields that vary slightly
from the basic format, and in some instructions the
operation performed does not follow the general
rules stated in this section. All such exceptions are
explicitly identified in the individual instruction de­
scriptions .. The format names express, in general terms, the
classes of operands which participate in the opera­
tion: RR denotes a register-to-register operation;
RX, a register-and-indexed-storage operation; RS, a
register-and-storage operation; SI, a storage-and­ operation; and SS, a storage-to-storage
operation. The S format denotes an operation using
an implied operand and storage.
The firHt byte and, in the S format, the first two
bytes of an instruction contain the operation code
(op code). For some instructions in the S format, all
or a portion of the second byte is ignored. The: first
two bits of the operation code specify the length and
format of an instruction, as follows:
Bit Positions Instruction Instruction 0-1 Length Format 00 One halfword RR 01 Two halfwords RX 10 Two halfwords RS/SI/S/RX 11 Three halfwords SS In the format illustration for each individual in­
struction description, the op-code field shows the op
code in hexadecimal representation. The hexadeci­
mal representation uses one graphic for a four-bit code, and therefore two graphics for an eight-bit
byte. The graphics 0-9 are used for the codes 0000- 1001; the graphics A-F are used for codes 1010- 1111. 20 System/370 Principles of Operation
The remaining fields in the format illustration for
each instruction are designated by code names, con­
sisting of a letter and possibly a subscript number.
The subscript number denotes the operand to which
the field applies.
Register Operands
In the RR, RX, and RS formats? the contents of the
register designated by the Rt field are called the first
operand. In the RR format, the Rl field designates
the register containing the second operand, and the
same register may be designated for the first and
second operand. In the RS format, the use of the R3
field depends on the instruction.
The R field designates a general register in the
general instructions and a floating-point register in
the floating-point instructions. In the instructions LOAD CONTROL and STORE CONTROL the R
field designates a control register.
Unless otherwise indicated in the individual in­
struction description, the register operand is one
register in length (32 bits for a general register or a
control register and 64 bits for a floating-point regis­
ter), and the second operand is the same length as
the first.
Immediate Operands
In the SI format, the contents of the eight-bit
immediate-data field, the Iz field of the instruction,
are used directly as the second operand. The B t and
Dt fields designate the first operand, which is one
byte in length. Storage Operands
In the SI and SS formats, the contents of the general
register designated by the Bt field are added to the
contents of the Dl field to form the first-operand
address. In the S, RS, and SS formats, the contents
of the general register designated by the Bl field are
added to the contents of the Dl field to form the
second-operand address. In the RX format, the con­
tents of the general registers designated by the X2
and Bl fields are added to the contents of the Dl field to form the second-operand address.
In the SS format, with two length fields given, Ll
specifies the number of additional operand bytes to
the right of the byte designated by the first-operand
address. Therefore, the length in bytes of the first
operand is 1-16, corresponding to a length code in
Ll of 0-15. Similarly, Ll specifies the number of
additional operand bytes to the right of the location
designated by the second-operand address. Results
replace the first operand, and are never stored out­
side the field specified by the address and length. In
the event the first operand is longer than the second,