malfunction that affects validity of a block of in­
formation is signaled only at the completion of data
transfer. The error condition normally does not pre­
maturely terminate or otherwise affect the execution
of the operation. Thus, there is no assurance that a
CCW read as data is valid until the operation is com­
pleted. If the CCW thus read is in error, use of the
CCW in the current operation may cause subsequent
data to be placed in wrong locations in main storage
with resultant destruction of its contents, subject to
the control of the protection system.
Command Chaining
During command chaining, the new CCW fetched
by the channel specifies a new I/O operation. The
channel fetches the new CCW and initiates the new
operation upon the receipt of the device-end signal
for the current operation. When command chaining
takes place, the completion of the current operation
does not cause an I/O interruption, and the count
indicating the amount of data transferred during the
current operation is not made available to the pro­
gram. For operations involving data transfer, the
new command always applies to the next block of
data at the device.
Command chaining takes place and the new oper­
ation is initiated only if no unusual conditions have
been detected in the current operation. In particular,
the channel initiates a new I/O operation·by com­
mand chaining upon receipt of a status byte contain­
ing only the following bit combinations: device end,
device end and status modifier, device end and chan­
nel end, device end and channel end and status modi­
fier. In the former two cases a channel end must
have been signaled before device end, with all other
status bits off. If a condition such as attention, unit
check, unit exception, incorrect length, program
check, or protection check has occurred, the se­
quence of operations is concluded, and the status
associated with the current operation causes an in­
terruption condition to be generated. The new CCW
in this case is not fetched. The incorrect-length con­
dition does not suppress command chaining if the
current CCW has the SLI flag on.
An exception to sequential chaining of CCWs
occurs when the I/O device presents the status­
modifier condition with the device-end signal. When
command chaining is specified and no unusual con­
ditions have been detected, the combination of
status-modifier and device-end bits causes the chan­
nel to fetch and chain to the CCW whose main­
storage address is 16 higher than that of the current
CCW.
When both command and data chaining are used,
the first CCW associated with operation speci-
fies the operation to be executed, and the last CCW
indicates whether another operation follows.
Programming Note
Command chaining makes it possible for the pro­
gram to initiate transfer of multiple blocks of data by
means of a single START I/O or START I/O FAST
RELEASE. It also permits a subchannel to be set up
for execution of auxiliary functions, such as position­
ing the disk-access mechanism, and for data-transfer
operations without interference by the program at
the end of each operation. Command chaining, in
conjunction with the status-modifier condition, per­
mits the channel to modify the normal sequence of
operations in response to signals provided by the I/O device.
Skipping
Skipping is the suppression of main-storage refer­
ences during an I/O operation. It is defined only for
read, read backward, and sense operations, and is
controlled by the skip flag, which can be specified
individually for each CCW. When the skip flag is
one, skipping occurs; when zero, normal operation
takes place. The setting of the skip flag is ignored in
all other operations.
Skipping affects only the handling of information
by the channel. The operation at the I/O device
proceeds normally, and information is transferred to
the channel. The channel keeps updating the count
but does not place the information in main storage.
Chaining is not precluded by skipping. In the case of
data chaining, normal operation is resumed if the
skip flag in the new CCW is zero.
No checking for invalid or protected data address­
es takes place during skipping.
Programming Note
Skipping, when combined with data chaining, per­
mits the program to place in main storage selected
portions of a block of information from an I/O de­
vice.
Program-Controlled Interruption
The program-controlled interruption (PCI) function
permits the program to cause an I/O interruption
during execution of an I/O operation. The function
is controlled by the PCI flag in the CCW. The flag
can be on either in the first CCW specified by
START I/O or START I/O FAST RELEASE or in
a CCW fetched during chaining. Neither the PCI
flag nor the associated interruption affects the execu­
tion of the current operation.
Whenever the PCI flag in the CCW is on, the
channel attempts to interrupt the program. When the
Input/Output Operations 215

first CCV{ associated with an operation the PCI flag, either initially or upon command chaining,
the interruption may occur as early as immediately
upon the initiation of the operation. The PCI flag in
a CCW on data chaining causes the inter­
ruption to occur after all data designated by the pre­
ceding CCW has been transferred. The time of the
interruption, however, depends on the model and the
current a(:tivity in the system and may be delayed
even if the channel is not masked. No predictable
relation exists between the time the interruption due
to the PCI flag occurs and the progress of data
transfer to or from the area designated by the CCW, but the fields within the CSW pertain to the same
instant of time.
If chaining occurs before the interruption due to
the PCI flag has taken place, the PCI condition is
carried over to the new CCW. This carryover occurs
both on data and command chaining and, in either
case, the condition is propagated through the trans­
fer in channel command. The PCI conditions are not
stacked; that is, if another CCW is fetched with a PCI flag before the interruption due to the PCI flag
of the previous CCW has occurred, only one inter­
ruption takes place.
A CS\V containing the PCI bit may be stored by
an interruption while the operation is still proceeding
or by an interruption, TEST I/O, or CLEAR I/O upon the termination of the operation. It cannot be
stored by TEST I/O while lthe subchannel is in the
working state.
When the CSW is stored by an interruption be­
fore the operation or chain of operations has been
concluded , the command address is eight higher
than the address of the current CCW, and the count
is unpredietable. All unit-status bits in the CSW are
zero. If the channel has detected any unusual condi­
tions, such as channel data check, program check, or
protection check by the time the interruption occurs,
the corresponding channel-status bit is on, although
the condition in the subchannel is not reset and is
indicated again upon the termination of the opera­
tion.
The presence of any unit-status bit in the CSW indicates that the operation or chain of operations
has been concluded. The CSW in this case has its
regular format with the PCI bit added.
However, when the interruption condition due to
the PCI flag has been delayed until the operation at
the subchamnel has been concluded, two interrup­
tions from the subchannel may still take place, with
the first interruption indicating and clearing the PCI condition alone, and the second providing the CSW associated with the ending status. Whether one or
two interruptions occur depends on the model and
216 System/370 Principles of Operation
on whether the PCI condition has been assigned the
highest priority for interruption at the time of con­
cluding. TEST I/O or CLEAR I/O addressed to the
device associated with an interruption condition in
the sub channel clears the PCI condition as well as
the one associated with the concluding.
The setting of the PCI flag is inspected in every CCW except those specifying transfer in channel,
where it is ignored. The PCI flag is also ignored
during initial program loading.
Programming Note
Since no unit-status bits are placed in the CSW asso­
ciated with the concluding of an operation of the
selector channel by HALT I/O or HALT DEVICE, the presence of a unit-status bit with the PCI bit is
not a necessary condition for the operation to be
concluded. When the selector channel contains the PCI bit at the time the operation is concluded by
HALT I/O or HALT DEVICE, the CSW associated
with the concluded operation is indistinguishable
from the CSW provided by an interruption during
execution of the operation.
Program-controlled interruption provides a means
of alerting the program of the progress of chaining
during an I/O operation. It permits programmed
dynamic main-storage allocation.
Channel Indirect Data Addressing Channel indirect data addressing (CIDA), a compan­
ion facility to dynamic address translation, provides
assistance in translating data addresses for I/O oper­
ations. It permits a single channel command word to
control the transmission of data that spans noncontig­
uous pages in real main storage. Channel indirect data addressing is specified by a
flag bit in the CCW which, when one, indicates that
the data address in the CCW is not used to directly
address data. Instead, the address points to a list of
words, called indirect-data-address words (IDAWs),
each of which contains an absolute address designat­
ing a data area within a 2,048-byte block of main
storage.
When the indirect data addressing bit in the CCW is one, bits 8-31 of the CCW specify the location of
the first indirect data address word (IDA W) to be
used for data transfer for the command. Additional
IDAWs, if needed for completing the data transfer
for the CCW, are in successive locations in storage.
The number of IDAWs required for a CCW is deter­
mined by the count field of the CCW and by the
data address in the initial IDAW. When, for exam­
ple, the CCW count field specifies 4,000 bytes and
the first IDA W specifies a location in the middle of a 2,048-byte block, three IDA Ws are required.