storage-operand update references. The refer­
ence bit is the only bit which is updated.
The record of references provided by the refer­
ence bit is not necessarily accurate, and the handling
of the reference bit is not subject to the concurrency
rules. However, in the majority of situations, refer­
ence recording approximately coincides with the
storage reference.
Storage-Operand References
A storage-operand reference is the fetching or stor­
ing of the explicit operand or operands in the main­
storage locations specified by the instruction.
During the execution of an instruction, all, or a
portion, of the storage operands for that instruction
may be fetched, intermediate results may be main­
tained for subsequent modification, and final results
may be temporarily held prior to placing them in
main storage. Stores caused by channels or by other CPUs do not necessarily affect these intermediate
results. Storage-operand references are of three
types: fetches, stores, and updates. Storage-Operand Fetch References
When the bytes of a storage operand participate in
the instruction execution only as a source, the refer­
ence to the location is called a storage-operand fetch
reference. A fetch reference is identified in the indi­
vidual instruction definition by indicating that the
access exception is for fetch.
All bits within a single byte of a fetch reference
are accessed concurrently. When an operand consists
of more than one byte, the bytes may be fetched
piecemeal a byte at a time from main storage. Unless
otherwise specified, the bytes are not necessarily
fetched in any particular order. The fetch reference
for the operands of some instructions is specified to
be concurrent Within a block. In this case, no stores
by any other 'CPU ,are permitted, to the same loca­
tion, between the fetches of the bytes within a block.
Storage-Operand Store References
When the bytes of a storage operand participate in
the instruction execution only to the extent of being
replaced by the result, the reference to the location
is called a storage-operand store reference. A store
reference is identified in the individual instruction definition by indicating that the access exception is
for store.
All bits within a single byte of a store reference
are accessed concurrently. When an operand consists
of more than one byte, the bytes may be stored
piecemeal a byte at a time into main storage. Unless
otherwise specified, the bytes are not necessarily
stored in any particular order. The store reference
for some instructions is specified to be concurrent
within a block. In this case, no stores or fetches by
any other CPU are permitted, to the same location,
between the stores of bytes within a block.
A CPU may delay storing results into main stor­
age. There is no defined limit on the length of time
that results may remain pending before they are
stored.
This delay does not affect the order in which re­
sults are placed in main storage. The results of one
instruction are placed in main storage after the re­
sults of all preceding instructions have been placed
in main storage and before any results of the suc­
ceeding instructions are stored. The results of any
one instruction are stored in the order specified for
that instruction.
A CPU does not fetch operands, or dynamic­
address-translation table entries, from a main­
storage location until all information destined for
that real main-storage location by that CPU has
been placed in main storage. Prefetched instructions
may appear to be updated prior to the information
appearing in storage.
The stores are necessarily completed only as a
result of a serializing operation and before the CPU enters the stopped state.
Storage-Operand Update References
In some instructions, the storage-operand location
participates both as a source and as a destination. In
these cases, the reference to the location consists
first of a fetch and subsequently of a store. The com­
bination of the two accesses is referred to as an up­
date reference. Instnictions such as MOVE ZONES, TRANSLATE, OR (OI), and ADD DECIMAL
cause an update to the first-operand location. In
most cases, no special interlock is provided between
the fetch and store, and accesses by channels and
other CPUs are permitted. An update reference is
identified in the individual instruction definition by
indicating that the access exception is for both fetch
and store. The fetch and store accesses associated
with an update reference are not necessarily made
contiguously, and it is possible for another CPU or
channel to make one or more interleaved accesses to
the same location. The interleaved accesses can be
either fetches or stores and can be associated with
either an update or an interlocked-update reference.
Three instructions perform an update which is
interlocked against accesses to the same location
during the execution of the instruction. The instruc­
tion TEST AND SET (TS) causes an interlocked
update, and the instructions COMPARE AND SW AP (CS) and COMPARE DOUBLE AND
Program Execution 25

SWAP (CDS) cause an interlocked update when
they set condition code o.
The fetch and store accesses associated with an
interlocked-update reference are not necessarily
made contiguously, but restrictions are made on
accesses to the location. The fetch access of an inter­
locked update by another CPU, and all store access­
es by another CPU, are prevented from occurring
between the fetch and the store accesses of an inter- I locked update. CPU fetches which are not part of an
interlocked update, including the fetches of a CS or
CDS instruction which results in condition code 1,
may be made from the location during the interlock
period. ][/0 accesses, either fetch or store, may oc­
cur during the interlock period.
Within the limitations of the above requirements,
the fetch and store accesses associated with an up­
date follow the same rules as the fetches and stores
described in the previous sections.
Programming Notes
When two CPUs attempt to update information at a
common main-storage location by an instruction that
causes fetching and subsequently storing of the up­
dated information, it is possible for both CPUs to
fetch the information and subsequently take the
store access. The change made by the first CPU to
store the result in such a case is lost. Similarly, if
one CPU updates the contents of a field but another CPU makes a store operation to that field between
the fetch and store parts of the update reference, the
effect of the store is lost. If, instead of a store ac­
cess, a CPU makes an interlocked-update reference
to the common storage field between the fetch and
store portions of an update due to another CPU, any
change in the contents produced by the interlocked
update is lost. Only those bytes which are included in the result
field of both operations are considered to be part of
the common main-storage location. However, all bits
within a Gommon byte are considered to be common
even if the bits modified by the two operations do
not overlap. As an example, if one CPU executes the
instruction OR (01) with the value 80 (hex) in the
immediate field and the other CPU executes AND
(NI) with an immediate operand of FE (hex) on the
same byte, one of the updates can be lost.
When the store access is part of an update refer­
ence by the CPU, the execution of the storing is not
contingent on whether the information to be stored
is different from the original contents of the loca­
tion. In particular, the contents of all designated
byte locations are replaced, and, for each byte in the
field, the entire contents of the byte are replaced.
26 System/370 Principles of Operation
An access to store information is performed, for
example, in the following cases:
a. Execution of the OR instruction (01 or OC) with a second operand of all zeros.
b. Execution of OR (OC) with the first-and
second-operand fields coinciding.
c. For those locations of the first operand of
TRANSLATE where the argument and func­
tion values are the same.
The instructions TEST AND SET, COMPARE AND SWAP, and COMPARE DOUBLE AND
SW AP facilitate updating of a common storage field
by two CPUs. In order for the change by either CPU not to be lost, both CPUs must use an instruction
providing an interlocked update. It is possible, how­
ever, for a channel to make an access to the same
storage location between the fetch and store por­
tions of an interlocked update.
Storage-Operand Consistency
Single-Access References With the exception of instructions operating on deci­
mal data, storage-operand references are single­
access references. A fetch reference is said to be a
single-access reference if the result of the operation
comprises a value fetched in a single access to each
byte of the data field. In the case of overlapping
operands, the location may be accessed once for
each operand. A store-type reference is said to be a
single-access reference if a single store access occurs
to each byte location within the data field. An up­
date reference is said to be single-access if the fetch
and store accesses are each single-access.
The storage references associated with the follow­
ing instructions are not necessarily single-access
references: the decimal-feature instructions and the
instructions CONVERT TO BINARY, CONVERT TO DECIMAL, MOVE WITH OFFSET, PACK, and UNPACK. When a storage-operand reference to a location is
not a single-access reference, the contents placed at
a byte location are not necessarily the same for each
store access; thus, intermediate results in a single
byte location may be observed by channels or other CPUs. Programming Note
When multiple fetch accesses are made to a single
byte that is being changed by a channel or another CPU, the result is not necessarily limited to that
which could be obtained by fetching the bits individ­
ually. For example, the process used in MULTIPLY DECIMAL may consist of repetitive additions and