The following four lists are of instructions arranged
by name, mnemonic, operation code, and feature.
Some models may offer instructions not appearing in
the lists, such as those provided for emulation or as
part of special or custom features ..
The operation code00, with a two-byte instruc
tion format, and the set of sixteen 16-bit operation
Thelistings in the Characteristics and Code columns mean:
A Access exceptions
A1 Addressing exceptiononly A2 Addressing and translation-specification exceptions only B PER branch event C Condition code is set CK CPU-timer and clock-comparator feature
D
Data exceptionDC Direct-control feature
DFDecimal-overflow exception
DKDecimal-divide exception
Appendix C. Lists of Instructions
codesB2EO to B2EF, with a four-byte instruction
format, are allocated for software uses where indica
tion of invalid operation is required. It is improbable
that these operation codes will ever be assigned to
an instruction implemented in theCPU. DM Depending on the model, DIAGNOSE may generate various program exceptions
and may change the condition code
E Exponent-overflow exception
EX Execute exception
FK Floating-point-divide exceptionFP Floating-point feature IF Fixed-point-overflowexception II Interruptible instruction I K Fixed-point-divide exception
L New condition codeloaded LS Significance exception
MPrivileged-operation exception MO Monitor event MP Multiprocessing feature PD Decimal feature PK PSW-key-handling feature
RPER general-register-alteration event
RR RR instruction formatRS RS instruction format
RX RX instruction formatS S instruction format SI SI in.struction format SO Special-operation exception SP Specification exception SS SS instruction format ST PER storage-alteration event SW Conditional-swapping feature
TRTranslation feature
U
Exponent-underflow exceptionXP Extended-precision floating-point feature
Bits 8-14 of the operation code are ignored+- Bits 8-15 of the operation code are ignored
$ Causesserialization $1 Causes serialization when the R
1 and R
2fields contain all ones and all zeros, respectively. Appendix C. Lists of Instructions 253
by name, mnemonic, operation code, and feature.
Some models may offer instructions not appearing in
the lists, such as those provided for emulation or as
part of special or custom features ..
The operation code
tion format, and the set of sixteen 16-bit operation
The
A Access exceptions
A1 Addressing exception
D
Data exception
DF
DK
Appendix C. Lists of Instructions
codes
format, are allocated for software uses where indica
tion of invalid operation is required. It is improbable
that these operation codes will ever be assigned to
an instruction implemented in the
and may change the condition code
E Exponent-overflow exception
EX Execute exception
FK Floating-point-divide exception
L New condition code
M
R
RR RR instruction format
RX RX instruction format
TR
U
Exponent-underflow exception
Bits 8-14 of the operation code are ignored
$ Causes
1 and R
2
