System Control Contents CPU States Wait and Running States Problem and Supervisor States. Stopped and Operating States. Control Modes BC Mode. EC Mode. Set-System-Mask Suppression Program Status Word Program Status Word Format in BC Mode Program Status Word Format in EC Mode
Exceptions Associated with the PSW .
Early Exception Recognition
Late Exception Recognition Control Registers
Key in Storage . Protection Protection Action
Accesses Protected Monitoring Program-Event Recording Control Register Allocation Operation Identification of Cause Priority of Indication Storage Area Designation
Program Events . Successful Branching I nstruction Fetching Storage Alteration .
General-Register Alteration I ndication of Events Concurrently with Other I nterruption Conditions
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T ime-of-Day Clock Format States Setting and I nspection of Value Clock Comparator CPU Timer Interval Timer Externally Initiated Functions
Resets CPU Reset Initial CPU Reset 1/0 System Reset Program Reset Initial Program Reset System-Clear Reset Power-On Reset . Store Status . I nitial Loading
This chapter provides the detailed description of a
number of facilities that provide for switching the
status of the system, for protecting a program from
interference by another program, for initiating cer­
tain operations externally, and, in general, for en­
hancing the efficiency, utility, and programmability
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The information determining the state and opera­
tion of the CPU resides in the program status word
(PSW) and in control registers. Additional status and
control information appears in low-order locations
of main storage. By providing a supervisor state and
a set of instructions that are valid only in the super­
visor state for changing the contents of the PSW and
System Control 29

control registers, a means is provided for avoiding
unauthorized or inadvertent change to the system
state.
The protection facility permits the protection of
the contents of main storage from destruction or
misuse caused by erroneous or unauthorized storing
or fetching by a program.
Four timing facilities are provided for measuring
time: the time-of -day clock permits indication of
calendar time with a resolution of 1 microsecond and
a period in excess of one hundred years; the clock
comparator permits a program to be alerted at a
particular instant of real time; and the CPU timer
and interval timer provide a means for a program to
be alerted after a specified time interval has elapsed.
Additionally, the following three facilities are
provided: monitoring, program-event recording, and
direct control. The monitoring facility is useful for
performing various measurement functions, whereas
program-event recording provides a means to assist
in debugging programs.
A set of externally initiated functions is provided
for initializing the system or for inspecting its state.
These functions include reset, store status, and initial
program loading. CPU States Excluding facilities that are provided for thc mainte­
nance of equipment, three types of state alternatives
in the CPU are distinguished: wait-running,
problem·-supervisor, and stopped-operating. These
states differ in the way they affect CPU functions
and in the way their status is indicated and switched.
Wait Q'nd Running States
In the wait state no instructions are processed,
whereas in the running state instruction fetching and
execution proceed in the normal manner. The CPU is interruptible in the wait state, provided it is ena­
bled for the interruption source.
The CPU is in the wait state when bit 14 of the PSW is one. When bit 14 is zero, the CPU is in the
running state.
The wait state is indicated in the operator section
of the system console by the wait light. No explicit
operator control is provided for changing the state.
The updating of timing facilities is not affected by
whether the CPU is in the wait or running state. ProbleJ'II and Supervisor States
The alternative between problem and supervisor
state determines whether the full set of instructions
is valid.
In the supervisor state all instructions are valid. In 30 System/370 Principles of Operation
the problem state only those instructions are valid
that cannot be used to affect system integrity and
that do not pertain to maintenance or model­
dependent functions. The instructions that are not
valid in the problem state are called privileged in­
structions; they include those which modify or in­
spect keys in storage, those which modify or inspect
the system control fields in the PSW and in control
registers, and those which pertain to timing facilities,
prefixing, inter-CPU communication, and
input/ output. A privileged instruction encountered
in the problem state constitutes a privileged-­
operation exception and causes a program interrup­
tion.
The CPU is in the problem state when bit 15 of
the PSW is one. When bit 15 is zero, the CPU is in
the supervisor state.
The updating of timing facilities is not affected by
whether the CPU is in the problem or supervisor
state.
Programming Notes
The CPU may be switched between wait-running
and problem-supervisor states only by introducing
an entire new PSW. This may be performed by LOAD PSW, an interruption (including a supervisor­
call interruption), or initial program loading.
The instruction LOAD PSW can be used to
switch from the supervisor to the problem state and
from the running to the wait state but not vice versa.
To allow return from an interruption-handling rou­
tine by LOAD PSW, the PSW for the interruption­
handling routine must specify the supervisor state.
In the wait state the CPU does not make repeated
references to main storage; therefore, wait state is
suitable for delaying operation until an interruption
occurs. References, however, may be made due to I/O operations and for updating the interval timer.
To leave wait state without manual intervention, the CPU must be enabled for the interruption source.
Stopped and Operating States
When the CPU is in the stopped state, instructions
and interruptions, other than the restart interruption,
are not executed. In the operating state, the CPU executes instructions and interruptions, subject to
the control of the wait bit and mask bits and in the
manner specified by the setting of the rate control
on the system console.
A change between the stopped and operating
states can be effected by manual intervention or by
use of the SIGNAL PROCESSOR instruction. The
stopped state is not controlled or identified by a bit
in the PSW.