each byte. To illustrate the use of MVZ with overlapping assume that the following data field is in storage: 800 805 I F1 I C2 I F31 C41 F5 I C61 Also assume that register 15 contains 00 00 08 00. The
instruction:
Machine Format Op Code L B, 0,
03 04 001 F 000 Assembler Format Op Code 01 (L, B1), 02 (B2)
MVZ 1(5,15),0(15)
propagates the zone from the byte at address 800 through
data field, so that the field becomes: 800 805 I F1 I F21 F31 F41 F51 F6 I Multiply (M, MR)
Assume that a number in register 5 is to be multiplied by
the contents of a word at address 3750. Initially:
The contents of register 4 are not significant
Register 5 contains 00 00 00 9 A = 15410 = the multiplicand
Register 11 contains 00 00 30 00 Register 12 contains 00 00 06 00 Storage locations 3750-3753 contain 00 00 00 83 = 13110
= the multiplier
The instruction required for performing the multiplica­
tion is:
Machine Format Op Code R1 X
2
B2 150 Assembler Format Op Code R
1
, 02 (X2' B2)
M 4, X'150' (11,12)
After the instruction is executed, registers 4 and 5 con­ tain the product:
Register 4 contains 00 00 00 00 Register 5 contains 00 00 4E CE = 20,174
10 Storage locations 3750-3753 are unchanged.
The RR format of the instruction can be used to square
the number in a register. Assume that register 7 contains 00 00 00 10 = 16
1 o. The instruction
Machine Format Op Code R1 R2 1C 16 I 7
Assembler Format Op Code R
l
, R2
MR 6,7 \< multiplies the number in register 7 by itself:
The product, 00 00 00 00 00 00 01 00 = 256
10
,
appears in registers 6 and 7. Multiply Halfword (MH)
The MULTIPLY HALFWORD instruction is used to multi­ ply the contents of a register by a halfword in storage. For
example, assume that:
Register 11 contains 00 00 00 15 = 21
1
0 = the multiplicand
Register 14 contains 000001 00 Register 15 contains 00002000 Storage locations 2102-2103 contain FF 09 = -39 = the multiplier
The instruction
Machine Format 002 Assembler Format Op Code R
1
, 02 (X
2
, B2)
MH 11,2(14,15)
multiplies the two numbers. The product, FF FF FC CD =
-819 1 0, replaces the original con tents of registe r 11. Only the low-order 32 bits of a product are stored in a
register; any high-order bits are lost. No program interrup­ tion occurs on overflow. OR (0, OR, 01, OC) When the Boolean operator OR is applied to two bits, the
result is one when either bit is one; otherwise, the result is
zero. When two bytes are ORed in System/370, each pair of
bits is handled separately; there is no connection from one
bit position to another. OR (01) A frequent use of the OR instruction is to set a particular
bit to one. For example, assume that storage location 4891
contains 0100 0010
2
• To set the rightmost bit of this byte
to one without affecting the other bits, the following
instruction can be used (assume that register 8 contains 00 00 48 90): Machine Format Op Code 12 96 01 Assembler Format Op Code 01 (B
1
), 12 01 1 (8),X'01' 001 Appendix I. Number Representation and Instruction-Use Examples 301

When this instruction is executed, the byte in storage is ORed with the immediate byte:
Location 4891: 0100 00102 Immediate byte: 0000 0001 2 Result: 0100 00112 The resulting byte with bit 7 set to one is stored in location
4891. Condition code 1 is set.
Pack (PACK) Assume that storage locations 1000-1004 contain the fol­
lowing zoned-decimal field that is to be converted to a
packed-decimal field and left in the same location: 1000 1004 Zoned Field I F1 I F21 F3 I F41 C5 I Also assume that register 12 contains 00 001000. After
the instruction
Machine Format ___ 00_0 __ ___ Assembler Format
PACK 10(5,12) ,0(5,12)
is executed!, the field in locations 1000-1004 is in the
packed-decimal format: 1000 1004 Packed Field 1 00 1 00 112 1 34 1 5C 1 Notes:
1. This example illustrates the operation of PACK when the
first- and second-operand fields overlap completely.
2. During the operation, the second operand was extended
with high-order zeros.
Shift Left Double (SLDA)
The SHIFT LEFT DOUBLE instruction is similar to SHIFT
LEFT SINGLE except that SLDA shifts the 63 bits (not
including the sign) of an even/odd register pair. The R 1 field
of this instruction must be even. For example, if the con­
tents of registers 2 and 3 are: 00 7F OA 72 FE DC BA 98 = 0000 0000 0111 1111 0000 1010 0111 0010 1111 1110 1101 1100 1011 1010 1001 1000 2 the instruc tion
Machine Format
01F 302 System/370 Principles of Operation
Assembler Format Op Code R
1
, 02 (8
2
) SLOA 2,31(0)
results in registers 2 and 3 both being left-shifted 31 bit po­
sitions, so that their new contents are:
7 F 6E 5 D 4C 00 00 00 00 = 0111 1111 0110 1110 0101 1101 0100 1100 0000 0000 0000 0000 0000 0000 0000 0000 2 In this case, a significant bit is shifted out of position 1, and
a fixed-point overflow interruption occurs (unless PSW bit
36 equals zero).
Shift Left Single (SLA)
Because the sign bit remains unchanged during an SLA op­
eration, this instruction performs an algebraic shift. For
example, if the contents of register 2 are: 00 7F OA 72 = 0000 0000 0111 1111 0000 1010 0111 0010 2 then the instruction
Machine Format 008 Assembler Format Op Code R
1
, 02 (82) SLA 2,8(0)
results in register 2 being shifted left eight bit positions so
that its new contents are:
7F OA 72 00 = 0111 1111 0000 1010 0111 0010 0000 0000 2 If a left shift of nine places had been specified, a significant
bit would have been shifted out of position 1, and a fixed­
point overflow interruption might have occurred (unless PSW bit 36 equaled zero).
Note that register 0 does not participate in the operation
and that the contents of the R3 field are ignored.
Store Multiple (STM)
Assume that the contents of general registers 14, 15, 0, and
1 are to be stored in consecutive words starting with loca­
tion 4050 and that:
Register 14 contains 00 00 25 63
Register 15 contains 00 01 27 36
Register 0 contains 12 43 00 62
Register 1 contains 73 26 12 57
Register 6 contains 00 00 40 00 The initial contents of locations 4050405 F are not significant
The STORE MULTIPLE instruction allows the use of just
one instruction to store the contents of the four registers
when it is written as: