for program-event recording purposes even if the
value stored is the same as the original value.
Implied locations that are referred to by the CPU in the process of timer updating, interruptions, exe­
cution of 110 instructions, and machine-check logout,
including the interval timer, PSW, CSW, and logout
locations, are not monitored. These locations, how­
ever, are monitored when information is stored there
explicitly by an instruction. Similarly, monitoring
does not apply to storing of data by a channel. The
key storage is not considered part of main storage,
and hence monitoring does not apply to alterations
made by SET STORAGE KEY and RESET REF­
ERENCEBIT.
The instruction STORE CHARACTERS UN­ DER MASK is not considered to alter the storage
location when the mask is zero.
The instructions COMPARE AND SWAP and COMP ARE DOUBLE AND SWAP are considered
to alter the second-operand location only when stor­
ing actually occurs.
The event is identified by setting bit 2 of the PER code to one.
General-Register Alteration
Alteration of the contents of a general register caus­
es a program-event interruption if bit 3 of the PER­ event-mask field is one, the alteration mask corre­
sponding to that general register is one, and the PER mask in the PSW is one.
The contents of a general register are considered
to have been altered whenever a new value is placed
into the register. Recognition of the event is not
contingent on the new value being different from the
previous one. A register-to-register format arithme­
tic or movement operation is considered to fetch the
contents of the register, perform the indicated opera­
tion, if any, and then replace the value in the regis­
ter. The register can be designated implicitly, such as
in TRANSLATE AND TEST and EDIT AND
MARK, or explicitly by an RR, RX, or RS instruc­
tion, including BRANCH AND LINK, BRANCH ON COUNT, BRANCH ON INDEX HIGH, and
BRANCH ON INDEX LOW OR EQUAL.
The instructions EDIT AND MARK and TRANS­
LATE AND TEST are considered to have altered
the contents of general register 1 only when these
instructions have caused information to be stored
into the register.
The instructions MOVE LONG and COMPARE LOGICAL LONG are always considered to alter the
contents of the four registers specifying the two op,er­ ands, including the cases where the padding charac­
ter is used, when both operands have a zero length,
or when condition code 3 is set for MOVE LONG. The instruction INSERT CHARACTERS UN­ DER MASK is not considered to alter the general
register when the mask is zero.
The instructions COMPARE AND SWAP and COMP ARE DOUBLE AND SWAP are considered
to alter the general register, or general register pair,
designated by Rl only when the contents are actual­
ly replaced, that is, when the first and second oper­
ands are not equal.
The event is identified by setting bit 3 of the PER code to one.
Programming Notes
The following are some specifics concerning general­
register alteration:
1. Register-to-register load instructions are con­
sidered to alter the register contents even when
both operand addresses designate the same
register.
2. Addition or subtraction of zero and multiplica­
tion or division by one are considered to con­
stitute alteration.
3. Logical and fixed-point shift operations are
considered to alter the register contents even
for shift amounts of zero.
4. The branching instructions BXH and BXLE
are considered to alter the first operand even
when zero is added to its value.
Indication of Events Concurrently with Other Interruption Conditions
The following rules govern the indication of program
events caused by an instruction that has caused also
a program exception or the monitor event to be indi­
cated, or that causes a supervisor-call interruption.
1. The indication of an instruction-fetching event
does not depend on whether the execution of
the instruction was completed, terminated, sup­
pressed, or nullified. The event, however, is not
indicated when an access exception prohibits
access to the first byte of the instruction.
When the first halfword of the instruction is
accessible but an access exception applies to
the second or third halfword of the instruction,
it is unpredictable whether the instruction­
fetching event is indicated.
2. When the operation is completed, the event is
indicated regardless of whether any program
exception or the monitoring event is recog­
nized.
3. Successful branching, storage alteration, or
general-register alteration are not indicated for
an operation or, in the case of the interruptible
System Control 43
instruction, for a unit of operation that is sup­
pressed or nullified.
4. When the execution of the instruction is termi­
nated, general-register and storage alteration is
indicated whenever the event has occuned. Additionally, a model may indicate the event if
the event would have occurred had the execu­
tion of the instruction been completed, even if
altering the contents of the result field is con­
tingent on operand values.
5. When LOAD PSW or SUPERVISOR CALL
causes a PER condition and at the same time
introduces a new PSW with the type of format
error that is recognized immediately after the PS"'N becomes active, the interruption code
identifies both the PER condition and the
specification exception. When these instruc­
tions introduce a PSW format error of the type
that is recognized as part of the execution of
the following instruction, the PSW is stored as
the old PSW without the exception being rec­
ognized.
The indication of program events concurrently
with other program interruption conditions is sum­
marized in the table "Indication of Program
Events."
Programming Notes
The execution of the interruptible instructions MOVE LONG (MVCL) and COMPARE LOGI­ CAL LONG (CLCL) can cause events for general­
register alteration and instruction fetch. Additional­
ly, MVeL can cause the storage-alteration event.
Since the execution of MVCL and CLCL can be
interrupted, a program event may be indicated more
than on(:e. It may be necessary, therefore, for a pro­
gram to remove the redundant event indications
from PER data. The following rules govern the
44 System/370 Principles of Operation
indication of the applicable events during execution
of these two instructions:
1. The instruction-fetching event is indicated
whenever the instruction is fetched for execu­
tion, regardless of whether it is the initial exe­
cution or resumption.
2. The general-register-alteration event is indicat­
ed on initial execution and on each resumption
and does not depend on whether or not the
register actually is changed.
3. The storage-alteration event is indicated only
when data has been stored in the monitored
area by the portion of the operation starting
with the last initiation and ending with the last
byte transferred before the interruption. No
special indication is provided on premature
interruptions as to whether the event will occur
again upon the resumption of the operation.
The event for address match on data storing
for a single byte location can be recognized
only once in the execution of MOVE LONG. The following is an outline of the general action a
program must take to delete the redundant entries in
the PER data for MOVE LONG and COMPARE LOGICAL LONG so that only one entry for each
complete execution of the instruction is obtained:
1. Check to see if the PER address is equal to the
instruction address in the old PSW and if the
last instruction executed was MVCL or CLCL.
2. If both conditions are met, delete instruction­
fetching and register-alteration events.
3. If both conditions are met, and the event is
storage alteration, delete the event if the cur­
rent destination-operand address is within the
monitored area and the count for the destina­
tion operand is not zero.
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