for program-event recording purposes even if the
value stored is the same as the original value.
Implied locations that are referred to by theCPU in the process of timer updating, interruptions, exe
cution of110 instructions, and machine-check logout,
including the interval timer,PSW, CSW, and logout
locations, are not monitored. These locations, how
ever, are monitored when information is stored there
explicitly by an instruction. Similarly, monitoring
does not apply to storing of data by a channel. The
key storage is not considered part of main storage,
and hence monitoring does not apply to alterations
made bySET STORAGE KEY and RESET REF
ERENCEBIT.
The instructionSTORE CHARACTERS UN DER MASK is not considered to alter the storage
location when the mask is zero.
The instructionsCOMPARE AND SWAP and COMP ARE DOUBLE AND SWAP are considered
to alter the second-operand location only when stor
ing actually occurs.
The event is identified by setting bit 2 of thePER code to one.
General-Register Alteration
Alteration of the contents of a general register caus
es a program-event interruption if bit 3 of thePER event-mask field is one, the alteration mask corre
sponding to that general register is one, and thePER mask in the PSW is one.
The contents of a general register are considered
to have been altered whenever a new value is placed
into the register. Recognition of the event is not
contingent on the new value being different from the
previous one. A register-to-register format arithme
tic or movement operation is considered to fetch the
contents of the register, perform the indicated opera
tion, if any, and then replace the value in the regis
ter. The register can be designated implicitly, such as
in TRANSLATE AND TEST and EDIT AND
MARK, or explicitly by an RR, RX, orRS instruc
tion, including BRANCH AND LINK, BRANCHON COUNT, BRANCH ON INDEX HIGH, and
BRANCHON INDEX LOW OR EQUAL.
The instructions EDIT AND MARK and TRANS
LATE AND TEST are considered to have altered
the contents of general register 1 only when these
instructions have caused information to be stored
into the register.
The instructionsMOVE LONG and COMPARE LOGICAL LONG are always considered to alter the
contents of the four registers specifying the twoop,er ands, including the cases where the padding charac
ter is used, when both operands have a zero length,
or when condition code 3 is set forMOVE LONG. The instruction INSERT CHARACTERS UN DER MASK is not considered to alter the general
register when the mask is zero.
The instructionsCOMPARE AND SWAP and COMP ARE DOUBLE AND SWAP are considered
to alter the general register, or general register pair,
designated by Rl only when the contents are actual
ly replaced, that is, when the first and second oper
ands are not equal.
The event is identified by setting bit 3 of thePER code to one.
Programming Notes
The following are some specifics concerning general
register alteration:
1. Register-to-register load instructions are con
sidered to alter the register contents even when
both operand addresses designate the same
register.
2. Addition or subtraction of zero and multiplica
tion or division by one are considered to con
stitute alteration.
3. Logical and fixed-point shift operations are
considered to alter the register contents even
for shift amounts of zero.
4. The branching instructions BXH and BXLE
are considered to alter the first operand even
when zero is added to its value.
Indication of Events Concurrently withOther Interruption Conditions
The following rules govern the indication of program
events caused by an instruction that has caused also
a program exception or the monitor event to be indi
cated, or that causes a supervisor-call interruption.
1. The indication of an instruction-fetching event
does not depend on whether the execution of
the instruction was completed, terminated, sup
pressed, or nullified. The event, however, is not
indicated when an access exception prohibits
access to the first byte of the instruction.
When the first halfword of the instruction is
accessible but an access exception applies to
the second or third halfword of the instruction,
it is unpredictable whether the instruction
fetching event is indicated.
2. When the operation is completed, the event is
indicated regardless of whether any program
exception or the monitoring event is recog
nized.
3. Successful branching, storage alteration, or
general-register alteration are not indicated for
an operation or, in the case of the interruptible
System Control 43
value stored is the same as the original value.
Implied locations that are referred to by the
cution of
including the interval timer,
locations, are not monitored. These locations, how
ever, are monitored when information is stored there
explicitly by an instruction. Similarly, monitoring
does not apply to storing of data by a channel. The
key storage is not considered part of main storage,
and hence monitoring does not apply to alterations
made by
ERENCEBIT.
The instruction
location when the mask is zero.
The instructions
to alter the second-operand location only when stor
ing actually occurs.
The event is identified by setting bit 2 of the
General-Register Alteration
Alteration of the contents of a general register caus
es a program-event interruption if bit 3 of the
sponding to that general register is one, and the
The contents of a general register are considered
to have been altered whenever a new value is placed
into the register. Recognition of the event is not
contingent on the new value being different from the
previous one. A register-to-register format arithme
tic or movement operation is considered to fetch the
contents of the register, perform the indicated opera
tion, if any, and then replace the value in the regis
ter. The register can be designated implicitly, such as
in TRANSLATE AND TEST and EDIT AND
MARK, or explicitly by an RR, RX, or
tion, including BRANCH AND LINK, BRANCH
BRANCH
The instructions EDIT AND MARK and TRANS
LATE AND TEST are considered to have altered
the contents of general register 1 only when these
instructions have caused information to be stored
into the register.
The instructions
contents of the four registers specifying the two
ter is used, when both operands have a zero length,
or when condition code 3 is set for
register when the mask is zero.
The instructions
to alter the general register, or general register pair,
designated by Rl only when the contents are actual
ly replaced, that is, when the first and second oper
ands are not equal.
The event is identified by setting bit 3 of the
Programming Notes
The following are some specifics concerning general
register alteration:
1. Register-to-register load instructions are con
sidered to alter the register contents even when
both operand addresses designate the same
register.
2. Addition or subtraction of zero and multiplica
tion or division by one are considered to con
stitute alteration.
3. Logical and fixed-point shift operations are
considered to alter the register contents even
for shift amounts of zero.
4. The branching instructions BXH and BXLE
are considered to alter the first operand even
when zero is added to its value.
Indication of Events Concurrently with
The following rules govern the indication of program
events caused by an instruction that has caused also
a program exception or the monitor event to be indi
cated, or that causes a supervisor-call interruption.
1. The indication of an instruction-fetching event
does not depend on whether the execution of
the instruction was completed, terminated, sup
pressed, or nullified. The event, however, is not
indicated when an access exception prohibits
access to the first byte of the instruction.
When the first halfword of the instruction is
accessible but an access exception applies to
the second or third halfword of the instruction,
it is unpredictable whether the instruction
fetching event is indicated.
2. When the operation is completed, the event is
indicated regardless of whether any program
exception or the monitoring event is recog
nized.
3. Successful branching, storage alteration, or
general-register alteration are not indicated for
an operation or, in the case of the interruptible
System Control 43