Direct Control
The direct-control feature provides two instructions,
READ DIRECT and WRITE DIRECT, and an
external-signal facility, consisting of six external
interruption lines. This feature operates indepen­
dently of the facilities for performing I/O operations.
The read and write instructions provide for the
transfer of a single byte of information, normally for
controlling or synchronizing purposes, between two
cable-connected processing units or a cable­
connected processing unit and external devices. Each
of the six external lines, when pulsed, sets up the
conditions for an external interruption.
Note: Some models provide the external-signal facili­
ty as a separate feature (without the READ DIRECT
and WRITE DIRECT instructions).
For a detailed description of direct control, see
the System/360 and System/370 Direct Control
and External Interruption Features--Original
Equipment Manufacturers' Information, GA22-
6845.
Time-of-Day Clock
The time-of-day clock provides a consistent measure
of elapsed time suitable for the indication of date
and time. The cycle of the clock is approximately
143 years.
In an installation with more than one CPU, de­
pending on the model, each CPU may have a sepa­
rate time-of -day clock, or more than one CPU may
share a dock. In all cases, each CPU accesses a sin­
gle clock.
Format
The time-of -day clock is a binary counter with a
format as shown in the following illustration. The bit
positions of the clock are numbered 0 to 63, corre­
sponding to the bit positions of an unsigned fixed­
point number of double precision. Time is measured
by incrementing the value of the clock, following the
rules for unsigned fixed-point arithmetic. c. ___ o 31 32 52
In the basic form, the clock is incremented by
adding a one in bit position 51 every microsecond.
46 System/370 Principles of Operation
63
In models having a higher or lower resolution, a dif­
ferent bit position is incremented at such a frequen­
cy that the rate of advancement of the clock is the
same as if a one were added in bit position 51 every
microsecond. The resolution of the time-of -day
clock is such that the incrementing rate is compara­
ble to the instruction execution rate of the model.
When more than one time-of -day clock exists in a
configured system, the stepping rates are synchro­
nized such that all time-of-day clocks in the configu­
ration are incremented at the exact same rate.
When incrementing of the clock causes a carry to
be propagated out of bit position 0, the carry is ig­
nored, and counting continues from zero on. The
program is not alerted, and no interruption condition
is generated as a result of the overflow.
The operation of the clock is not affected or in­
hibited by any normal activity or event in the sys­
tem. The clock runs when the CPU is in the wait or
stopped state, or in the instruction-step, single-cycle,
or test mode, and its operation is not affected by CPU, initial-CPU, program, initial-program, or
system-clear resets or by the IPL procedure. De­
pending on the implementation, the clock mayor
may not run with the CPU power off.
States
The following states are distinguished for the time­
of -day clock: set, not set, stopped, error, and not
operational. The state determines the condition code
set by STORE CLOCK. The clock is said to be run­
ning when it is in either the set or not-set state.
The clock is in the not-operational state when its
power is down or when it is disabled for mainte­
nance. It depends on the model if the clock can be
placed in this state.
When the power for the clock is turned on, the_
value of the clock is set to zero, and the clock enters
the not-set state. With the clock in this state, STORE CLOCK causes condition code 1 to be set.
The clock enters the stopped state when SET CLOCK causes the clock's contents to be set, that
is, when SET CLOCK is executed without encoun­
tering any exceptions and with the TOD-clock
switch in the enable-set position. The clock can be
placed in the stopped state from the set, not-set, and
error states. The clock is not incremented while in
the stopped state. When the clock is in the stopped
state, STORE CLOCK causes the value of the
stopped clock to be stored and condition code 3 to be
set. This is distinguished from the not-operational
state, where condition code 3 is set and a value of
zero is stored.
The clock enters the set state only from the
stopped state. This is under control of the time-of-day

\
clock synchronization control bit, which is contained
in control register 0, bit position 2. The initial value
of this bit is zero. When the bit is zero or the clock­
synchronization facility is not installed, the clock
enters the set state at the completion of the SET CLOCK instruction. When the bit is one, the clock
remains in the stopped state until either the bit is set
to zero or until any other running time-of-day clock
in the configured system is incremented to a value of
all zeros in bit positions 32-63. Incrementing of the
clock begins with the first stepping pulse after the
clock enters the set state. If a clock is set to a value
of all zeros in bit positions 32-63 and enters the set
state as the result of a signal from another clock, bits
32-63 of the two clocks are in synchronism. The
In a system where more than one CPU accesses
the same clock, SET CLOCK is interlocked such
that the entire contents appear to be updated at
once. That is, if SET CLOCK instructions are issued
simultaneously by two CPUs, the final result is ei­
ther one or the other value. If SET CLOCK is issued
on one CPU and STORE CLOCK on the other, the
result is either the entire old value or the entire new
value. When SET CLOCK is issued by one CPU, a STORE CLOCK issued on another CPU may find
the clock in the stopped state even when the time­
of-day clock synchronization control bit is zero. Since the clock enters the set state before increment­
ing, the first STORE CLOCK issued after the clock enters the set state may still find the original value i introduced by SET CLOCK. SET CLOCK instruction results in condition code 0
when the clock is set, regardless of whether the clock -I­ remains in the stopped state or enters the set state at Programming Notes Rl the completion of the instruction. /I Bit position 31 of the clock is incremented every
The clock enters the error state when a malfunc- \-1.048576 seconds; hence for timing applications
tion is detected that is likely to have affected the involving human responses, the high-order clock
validity of the clock's value. A timing-facility dam-word may provide sufficient resolution.
age machine-check interruption condition is generat-To provide compatible operation from one system
ed whenever the clock enters the error state. When to another requires the establishing of a standard STORE CLOCK is executed with the clock in the time origin, or epoch; that is, the calendar date and
error state, condition code 2 is set.
Setting and Inspection of Value The clock can be inspected by means of the instruc­
tion STORE CLOCK which causes the current 64-
bit clock value to be stored in main storage. The
execution of STORE CLOCK is interlocked such
that successive executions, either from the same CPU or from different CPUs, do not provide the
same clock value if the clock is running. In multi­ configurations, this unique value may be
obtained by storing additional bits of lower order
than the resolution of the clock. These bits are not ,stored when the clock is in the stopped or not­
operational state. With the exception of these bits,
the clock provides only those bits which are incre­
mented. Zeros are stored for the low-order bits not
provided by the clock.
The clock can be set to a specific value by means
of SET CLOCK, which causes the current clock
value to be replaced by the operand designated by
the instruction. The instruction SET CLOCK causes
the value of the clock to be changed only when the TOD-clock switch on the system console is set to
permit changing the value of the clock. In a multi­
processing system, the TOD-clock switch in each CPU which is configured to this CPU is ORed with
the switch on this CPU. Thus, the operator can ena­
ble the setting of all clocks in the configuration by
using the switch ,of any CPU in the configuration.
time to which a clock value of zero corresponds.
January 1, 1900, 0 A.M. Greenwich Mean Time is
recommended as the standard epoch for the clock,
although some early support of the TOD clock is not
based on this epoch.
A program using the clock's value as a time-of­
day and calendar indication may have to be aware of
the support under which it is running. With the
standard epoch, bit 0 of the TOD clock turns on
May 11, 1971 at 11:56:53.685248 A.M. GMT.
Normally a test of the high-order bit is sufficient to
determine if the TOD clock value is the standard
epoch: a one in this bit position indicates the
standard epoch.
In converting to or from the current date or time,
the program assumes each day to be 86,400 seconds.
It does not take into account "leap" seconds added
because of time-correction standards.
Because of the inaccuracies in setting the clock
value on the basis of a synchronization signal pro­
vided by the operator, the low-order bit positions of
the clock, expressing fractions of seconds, normally
are not valid as indications of time of day. However,
they permit elapsed time measurements of high reso­
lution.
Clock Comparator
The clock comparator provides a means of causing an interruption when the time-of -day clock has
passed a value specified by the program.
System Control 47