\
clock synchronization control bit, which is contained
in control register 0, bit position 2. The initial value
of this bit is zero. When the bit is zero or the clock­
synchronization facility is not installed, the clock
enters the set state at the completion of the SET CLOCK instruction. When the bit is one, the clock
remains in the stopped state until either the bit is set
to zero or until any other running time-of-day clock
in the configured system is incremented to a value of
all zeros in bit positions 32-63. Incrementing of the
clock begins with the first stepping pulse after the
clock enters the set state. If a clock is set to a value
of all zeros in bit positions 32-63 and enters the set
state as the result of a signal from another clock, bits
32-63 of the two clocks are in synchronism. The
In a system where more than one CPU accesses
the same clock, SET CLOCK is interlocked such
that the entire contents appear to be updated at
once. That is, if SET CLOCK instructions are issued
simultaneously by two CPUs, the final result is ei­
ther one or the other value. If SET CLOCK is issued
on one CPU and STORE CLOCK on the other, the
result is either the entire old value or the entire new
value. When SET CLOCK is issued by one CPU, a STORE CLOCK issued on another CPU may find
the clock in the stopped state even when the time­
of-day clock synchronization control bit is zero. Since the clock enters the set state before increment­
ing, the first STORE CLOCK issued after the clock enters the set state may still find the original value i introduced by SET CLOCK. SET CLOCK instruction results in condition code 0
when the clock is set, regardless of whether the clock -I­ remains in the stopped state or enters the set state at Programming Notes Rl the completion of the instruction. /I Bit position 31 of the clock is incremented every
The clock enters the error state when a malfunc- \-1.048576 seconds; hence for timing applications
tion is detected that is likely to have affected the involving human responses, the high-order clock
validity of the clock's value. A timing-facility dam-word may provide sufficient resolution.
age machine-check interruption condition is generat-To provide compatible operation from one system
ed whenever the clock enters the error state. When to another requires the establishing of a standard STORE CLOCK is executed with the clock in the time origin, or epoch; that is, the calendar date and
error state, condition code 2 is set.
Setting and Inspection of Value The clock can be inspected by means of the instruc­
tion STORE CLOCK which causes the current 64-
bit clock value to be stored in main storage. The
execution of STORE CLOCK is interlocked such
that successive executions, either from the same CPU or from different CPUs, do not provide the
same clock value if the clock is running. In multi­ configurations, this unique value may be
obtained by storing additional bits of lower order
than the resolution of the clock. These bits are not ,stored when the clock is in the stopped or not­
operational state. With the exception of these bits,
the clock provides only those bits which are incre­
mented. Zeros are stored for the low-order bits not
provided by the clock.
The clock can be set to a specific value by means
of SET CLOCK, which causes the current clock
value to be replaced by the operand designated by
the instruction. The instruction SET CLOCK causes
the value of the clock to be changed only when the TOD-clock switch on the system console is set to
permit changing the value of the clock. In a multi­
processing system, the TOD-clock switch in each CPU which is configured to this CPU is ORed with
the switch on this CPU. Thus, the operator can ena­
ble the setting of all clocks in the configuration by
using the switch ,of any CPU in the configuration.
time to which a clock value of zero corresponds.
January 1, 1900, 0 A.M. Greenwich Mean Time is
recommended as the standard epoch for the clock,
although some early support of the TOD clock is not
based on this epoch.
A program using the clock's value as a time-of­
day and calendar indication may have to be aware of
the support under which it is running. With the
standard epoch, bit 0 of the TOD clock turns on
May 11, 1971 at 11:56:53.685248 A.M. GMT.
Normally a test of the high-order bit is sufficient to
determine if the TOD clock value is the standard
epoch: a one in this bit position indicates the
standard epoch.
In converting to or from the current date or time,
the program assumes each day to be 86,400 seconds.
It does not take into account "leap" seconds added
because of time-correction standards.
Because of the inaccuracies in setting the clock
value on the basis of a synchronization signal pro­
vided by the operator, the low-order bit positions of
the clock, expressing fractions of seconds, normally
are not valid as indications of time of day. However,
they permit elapsed time measurements of high reso­
lution.
Clock Comparator
The clock comparator provides a means of causing an interruption when the time-of -day clock has
passed a value specified by the program.
System Control 47
Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 In a multiprocessing system, each CPU has a sep­
arate clock comparator.
The clock comparator has the same format as the
time-of-day clock. In the basic form, the clock com­
parator consists of bits 0-47, which are compared
with the corresponding bits of the time-of-day clock.
In some models, higher resolution is obtained by
comparing more than 48 bits. When the resolution of
the time-of -day clock is less than that of the clock
comparator, the contents of the clock comparator
are compared with the clock value as this value
would be stored by STORE CLOCK. Thli! clock comparator causes an external inter­
ruption with the interruption code 1004 (hex). A re­
quest for a clock comparator interruption exists when­
ever either of the following conditions exists: The time-of -day clock is running and the value
of the clock comparator is less than the value
in the compared portion of the time-of-day
dock, both comparands being considered bina­
ry unsigned quantities The clock comparator is installed and the time­ of -day clock is in the error state or not opera­ Honal A request for a clock-comparator interruption
does not remain pending when the value of the clock
comparator is made equal to or larger than that of
the time-of -day clock or when the value of the time­
of-day clock is made less than the clock-comparator
value.. The latter may occur as a result of the time­
of-day clock either being set or wrapping to zero.
The clock comparator can be inspected by means
of the: instruction STORE CLOCK COMP ARA­ TOR and can be set to a specific value by means of
the SET CLOCK COMPARATOR instruction.
The contents of the clock comparator are initial­
ized to zero.
Programming Note
The instruction STORE CLOCK may store a value
which is larger than that in the clock comparator,
even though the CPU is enabled for the clock com­
parator interruption. This is because the time-of-day
clock: may be incremented one or more times be­
tween the instants when instruction execution is
begun and when the clock value is accessed. Howev­
er, in this situation the interruption occurs at the
completion of the execution of the instruction.
An interruption request for clock comparator
persists as long as the clock comparator value is less
than that of the TOO clock or as long as the TOO clock is not operational or in the error state. In view
of this, after an external interruption for clock com­
parator has occurred, either the value of the clock
comparator has to be replaced or the clock-
48 System/370 Principles of Operation comparator submask has to be set to zero before the CPU is again enabled for external interruptions. Otherwise, loops of external interruptions are
formed. CPU Timer
The CPU timer provides a means for measuring
elapsed CPU time and for causing an interruption
when a prespecified amount of time has elapsed.
In a multiprocessing system, each CPU has a sep­
arate CPU timer.
The CPU timer is a binary counter with a format
which is the same as that of the time-of -day clock,
except that bit 0 is considered a sign. In the basic
form, the CPU timer is decremented by subtracting a
one in bit position 51 every microsecond. In models
having a higher or lower resolution, a different bit
position is decremented at such a frequency that the
rate of reduction of the CPU timer is the same as if a
one were subtracted in bit position 51 every micro­
second. The resolution of the CPU timer is such that
the stepping rate is comparable to the instruction
execution rate of the model.
The CPU timer causes an external interruption
with the interruption code 1005 (hex). A request for
a CPU-timer interruption exists whenever the value
in the CPU timer is negative (bit 0 of the CPU timer
is one). The request does not remain pending when
the CPU-timer value is made positive.
When both the CPU timer and the time-of -day
clock are running, the stepping rates are synchro­
nized such that both are stepped at the same rate.
Normally the decrementing of the CPU timer is not
affected by concurrent I/O activity. However, in
some models the CPU timer may stop during ex­
treme I/O activity and other similar interference
situations. In these cases, the time recorded by the CPU timer provides a more accurate measure of the CPU time used by the program than that which
would have been recorded had the CPU timer con­
tinued to step.
The CPU timer is decremented when the CPU is
executing instructions, during the wait state, and
during initial program loading, but it is not decre­
mented when the CPU is in the stopped state. When
the rate switch on the system console is in the
instruction-step position, the CPU timer is decre­
mented only during the time in which the CPU is
actually performing a unit of operation. Depending
on the model, the CPU timer mayor may not be
decremented when the time-of -day clock is in the
error, stopped, or not-operational state or when the CPU is in the check-stop state.
The CPU timer can be inspected by means of the
instruction STORE CPU TIMER and can be set to a
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