\
clock synchronization control bit, which is contained
in control register 0, bit position 2. The initial value
of this bit is zero. When the bit is zero or the clock
synchronization facility is not installed, the clock
enters the set state at the completion of theSET CLOCK instruction. When the bit is one, the clock
remains in the stopped state until either the bit is set
to zero or until any other running time-of-day clock
in the configured system is incremented to a value of
all zeros in bit positions 32-63. Incrementing of the
clock begins with the first stepping pulse after the
clock enters the set state. If a clock is set to a value
of all zeros in bit positions 32-63 and enters the set
state as the result of a signal from another clock, bits
32-63 of the two clocks are in synchronism. The
In a system where more than oneCPU accesses
the same clock,SET CLOCK is interlocked such
that the entire contents appear to be updated at
once. That is, ifSET CLOCK instructions are issued
simultaneously by twoCPUs, the final result is ei
ther one or the other value. IfSET CLOCK is issued
on oneCPU and STORE CLOCK on the other, the
result is either the entire old value or the entire new
value. WhenSET CLOCK is issued by one CPU, a STORE CLOCK issued on another CPU may find
the clock in the stopped state even when the time
of-day clock synchronization control bit is zero.Since the clock enters the set state before increment
ing, the firstSTORE CLOCK issued after the clock enters the set state may still find the original value i introduced by SET CLOCK. SET CLOCK instruction results in condition code 0
when the clock is set, regardless of whether the clock-I remains in the stopped state or enters the set state at Programming Notes Rl the completion of the instruction. /I Bit position 31 of the clock is incremented every
The clock enters the error state when a malfunc-\-1.048576 seconds; hence for timing applications
tion is detected that is likely to have affected the involving human responses, the high-order clock
validity of the clock's value. A timing-facility dam-word may provide sufficient resolution.
age machine-check interruption condition is generat-To provide compatible operation from one system
ed whenever the clock enters the error state. When to another requires the establishing of a standardSTORE CLOCK is executed with the clock in the time origin, or epoch; that is, the calendar date and
error state, condition code 2 is set.
Setting and Inspection ofValue The clock can be inspected by means of the instruc
tionSTORE CLOCK which causes the current 64-
bit clock value to be stored in main storage. The
execution ofSTORE CLOCK is interlocked such
that successive executions, either from the sameCPU or from different CPUs, do not provide the
same clock value if the clock is running. In multi configurations, this unique value may be
obtained by storing additional bits of lower order
than the resolution of the clock. These bits are not,stored when the clock is in the stopped or not
operational state. With the exception of these bits,
the clock provides only those bits which are incre
mented. Zeros are stored for the low-order bits not
provided by the clock.
The clock can be set to a specific value by means
ofSET CLOCK, which causes the current clock
value to be replaced by the operand designated by
the instruction. The instructionSET CLOCK causes
the value of the clock to be changed only when theTOD-clock switch on the system console is set to
permit changing the value of the clock. In a multi
processing system, theTOD-clock switch in each CPU which is configured to this CPU is ORed with
the switch on thisCPU. Thus, the operator can ena
ble the setting of all clocks in the configuration by
using the switch,of any CPU in the configuration.
time to which a clock value of zero corresponds.
January 1, 1900, 0 A.M. Greenwich Mean Time is
recommended as the standard epoch for the clock,
although some early support of theTOD clock is not
based on this epoch.
A program using the clock's value as a time-of
day and calendar indication may have to be aware of
the support under which it is running. With the
standard epoch, bit 0 of theTOD clock turns on
May 11, 1971 at 11:56:53.685248 A.M. GMT.
Normally a test of the high-order bit is sufficient to
determine if theTOD clock value is the standard
epoch: a one in this bit position indicates the
standard epoch.
In converting to or from the current date or time,
the program assumes each day to be 86,400 seconds.
It does not take into account"leap" seconds added
because of time-correction standards.
Because of the inaccuracies in setting the clock
value on the basis of a synchronization signal pro
vided by the operator, the low-order bit positions of
the clock, expressing fractions of seconds, normally
are not valid as indications of time of day. However,
they permit elapsed time measurements of high reso
lution.
Clock Comparator
The clock comparator provides a means of causingan interruption when the time-of -day clock has
passed a value specified by the program.
System Control 47
clock synchronization control bit, which is contained
in control register 0, bit position 2. The initial value
of this bit is zero. When the bit is zero or the clock
synchronization facility is not installed, the clock
enters the set state at the completion of the
remains in the stopped state until either the bit is set
to zero or until any other running time-of-day clock
in the configured system is incremented to a value of
all zeros in bit positions 32-63. Incrementing of the
clock begins with the first stepping pulse after the
clock enters the set state. If a clock is set to a value
of all zeros in bit positions 32-63 and enters the set
state as the result of a signal from another clock, bits
32-63 of the two clocks are in synchronism. The
In a system where more than one
the same clock,
that the entire contents appear to be updated at
once. That is, if
simultaneously by two
ther one or the other value. If
on one
result is either the entire old value or the entire new
value. When
the clock in the stopped state even when the time
of-day clock synchronization control bit is zero.
ing, the first
when the clock is set, regardless of whether the clock
The clock enters the error state when a malfunc-
tion is detected that is likely to have affected the involving human responses, the high-order clock
validity of the clock's value. A timing-facility dam-word may provide sufficient resolution.
age machine-check interruption condition is generat-To provide compatible operation from one system
ed whenever the clock enters the error state. When to another requires the establishing of a standard
error state, condition code 2 is set.
Setting and Inspection of
tion
bit clock value to be stored in main storage. The
execution of
that successive executions, either from the same
same clock value if the clock is running. In multi
obtained by storing additional bits of lower order
than the resolution of the clock. These bits are not
operational state. With the exception of these bits,
the clock provides only those bits which are incre
mented. Zeros are stored for the low-order bits not
provided by the clock.
The clock can be set to a specific value by means
of
value to be replaced by the operand designated by
the instruction. The instruction
the value of the clock to be changed only when the
permit changing the value of the clock. In a multi
processing system, the
the switch on this
ble the setting of all clocks in the configuration by
using the switch
time to which a clock value of zero corresponds.
January 1, 1900, 0 A.M. Greenwich Mean Time is
recommended as the standard epoch for the clock,
although some early support of the
based on this epoch.
A program using the clock's value as a time-of
day and calendar indication may have to be aware of
the support under which it is running. With the
standard epoch, bit 0 of the
May 11, 1971 at 11:56:53.685248 A.M. GMT.
Normally a test of the high-order bit is sufficient to
determine if the
epoch: a one in this bit position indicates the
standard epoch.
In converting to or from the current date or time,
the program assumes each day to be 86,400 seconds.
It does not take into account
because of time-correction standards.
Because of the inaccuracies in setting the clock
value on the basis of a synchronization signal pro
vided by the operator, the low-order bit positions of
the clock, expressing fractions of seconds, normally
are not valid as indications of time of day. However,
they permit elapsed time measurements of high reso
lution.
Clock Comparator
The clock comparator provides a means of causing
passed a value specified by the program.
System Control 47