The value of the timer is accessible by fetching
the word at location 80 as an operand, provided the
location is not protected against fetching. The 32-bit
timer value may be changed at any time by storing a
new value at location 80. When location 80 is pro­
tected, any attempt to change the value of the timer
causes a program interruption for protection excep­
tion. When protection exception is indicated, the
timer value remains unchanged.
The value of the timer may be changed without
losing the real-time count by loading the new value
in byte locations 84-87 and then shifting bytes 80- 87 into byte locations 76-83 by means of the in­
struction MOVE (MVC), thus placing in a single
operation the new timer value into word location 80 and making the old value available at location 76.
The MVC instruction may designate locations 76-87
by real addresses 76-87 or by any logical addresses
that translate to real addresses 76-87.
When the contents of the timer are fetched by
another CPU or by a channel or are used as a source
of an instruction, the result is unpredictable. Similar­
ly, storing by the channel or by another CPU at loca­
tion 80 causes the contents of the timer to be unpre­
dictable.
The timer value is not decremented when the CPU is not in the operating state, or when the rate
switch 0111 the system console is set to the
instruction-step position.
Programming Notes
The interval timer, in association with a program,
can serve both as a real-time clock and as an interval
timer.
If any means other than the instruction MOVE (MVC) are used to interrogate and then replace the
value of the timer, including MOVE LONG or two
separate instructions, the program may lose a time
increment if an updating cycle occurs between fetch­
ing and storing.
When the value of the interval timer is to be re­
corded on an 110 device, the program should first
store the timer value in a temporary storage location
to which the 110 operation subsequently refers.
When the channel fetches the timer value directly
from location 80, the value obtained is unpredicta­
ble.
Externally Initiated Functions
Resets
Two types of CPU-reset functions are provided: CPU reset and initial CPU reset. By combining the
two CPU-reset functions with the I/O-system-reset
function and clearing of storage, the following three
system resets are provided: program reset, initial
program reset, and system-clear reset. The table "Manual Initiation of System Resets" at the end of
the description of resets summarizes how each type
of system reset is manually initiated. Power-on reset
is performed as part of powering on. CPU reset provides a means of clearing
equipment-check indications and the resultant un­
predictability, if any, in the CPU state with the least
amount of information destroyed. It is intended in
particular for clearing check conditions when the
system state is to be preserved for analysis or re­
sumption of the operation.
Initial CPU reset performs the same functions as CPU reset but additionally initializes the contents of
control fields. In particular, it initializes the prefix
and control registers, which is normally necessary for
initial program loading.
Function Performed On 1
Position of Enable- CPU on Which Key Was Other CPUs Configured for
Propagation of Manual Reset Key Activated System-Clear Key Activated System reset • Without store-status facility Normal Initial-program reset • With store-status facility Normal Program reset Program reset System reset Clf!ar System-clear reset System-clear reset
Load Normal I nitial-program reset, followed Program reset
by IPL Load Clear System-clear reset, followed System-clear reset
by IPL Explanation: * This situation cannot occur, since the store-status facility is provided in a CPU equipped for multiprocessing.
1 Activation of the system-reset or load key may change the configuration, including the connection with channels, storage units,
and other CPUs.
Manual Initiation of System Resets 50 System/370 Principles of Operation

Program reset and initial program reset cause CPU reset and initial CPU reset, respectively, to be
performed, and additionally cause I/O system reset
to be performed. Sy.rtem-clear reset causes initial program reset to
be performed and, additionally, initializes or clears
all registers and storage locations whose contents
can be modified by a program. Such clearing is use­
ful in debugging programs and to ensure user priva­
cy.
Power-on reset initializes the contents of all con­
trol fields and either clears to zeros with valid
checking-block code, or introduces valid checking­
block code on, registers and storage locations that
lose their contents when power is down. It eliminates
the possibility of machine-check conditions due to
random values introduced by powering on. CPU Reset CPU reset causes the following actions:
1. The execution of the current instruction or
other processing sequence, such as interrup­
tion, is terminated, and all program and
supervisor-call interruption conditions are
cleared.
2. Pending external-interruption conditions are
cleared.
3. Pending machine-check-interruption conditions
and error indications are cleared.
4. The translation-lookaside buffer is cleared of
entries.
5. Any buffers containing prefetched instructions
or operands or results due to be stored are
cleared of entries.
6. The CPU is placed in the stopped state after
actions 1-5 have been completed. See the table "Summary of Reset Action" for a
detailed description of the effect of this reset on
other parts of the system.
The CPU-reset function is performed as part of
the three system resets and when the CPU accepts
the CPU-reset order specified by a SIGNAL PROC­ ESSOR instruction addressing this CPU. On some CPUs, model-dependent controls may be provided
for initiating CPU reset.
Initial CPU Reset
Initial CPU reset causes CPU reset to be performed
and additionally causes the following actions prior to
placing the CPU in the stopped state:
1. The contents of the PSW, prefix, CPU timer,
and clock comparator are set to zeros with
valid checking-block code.
2. The contents of control registers are set to their
initial values with valid checking-block code.
By setting the contents of the PSW to zero, the
initial-CPU-reset function causes the PSW to assume
the BC-mode format. The contents of the
instruction-length-code and interruption-code fields
remain unpredictable, as these values are not re­
tained when a new PSW is introduced. See the table "Summary of Reset Action" for a
detailed description of the effect of this reset on
other parts of the system.
The initial-CPU-reset function is performed as
part of the initial-program and system-clear resets
and when the CPU accepts the initial-CPU-reset
order specified by a SIGNAL PROCESSOR instruc­
tion addressing this CPU. On some CPUs, model­
dependent controls may be provided for initiating
initial CPU reset. I/O System Reset I/O system reset causes the I/O-system-reset func­
tion to be performed in the channel (see the chapter "I/O Operations"). As part of this reset, pending
I/O-interruption conditions are cleared and system
reset is signaled to all control units and devices con­
figured to the channel.
The effect of system reset on I/O control units
and devices and the resultant control-unit and device
state are described in the appropriate Systems Refer­
ence Library (SRL) or System Library (SL) publica­
tion. In general, a system reset resets only those
functions in a shared control unit or device that are
associated with the CPU signaling the reset.
The I/O-system-reset function is performed as
part of the three system resets and normally cannot
be initiated by itself.
Program Reset Program reset causes CPU reset to be performed
and causes I/O system reset to be performed in all
channels configured to the CPU. See the table "Summary of Reset Action" for a detailed descrip­
tion of the effect of the reset on other parts of the
system.
Execution of the program-reset function is initiat­
ed in a CPU by any of the following:
1. On a model that has the store-status facility
installed, by activating the system-reset key on
that CPU with the enable-system-clear key in
the normal position.
2. By activating the following keys in any other
configured CPU in a multiprocessing system: • The system-reset key with the enable-system­
clear key in the normal position, or
System Control 51