main storage, including the checking-block code,
remain unchanged.
Store Status
The store-status facility includes the following:
1. A ehange to the operation of the system-reset
key when the enable-system-clear key is in the
normal position. With the store-status facility
installed, pressing the system-reset key causes
a program reset; without this facility, initial
program reset is performed.
2. An operator-initiated store-status function.
The store-status operation consists in placing the
contents of the current PSW and the program­
addressable registers in permanently assigned loca­
tions within the first 512 bytes of main storage. In
the BC mode, the instruction-length code in the PSW is unpredictable, and an interruption code of
zero is stored. The information provided for control
register positions not associated with an installed
facility is unpredictable. If the CPU timer, clock
comparator, prefix register, or floating-point facility
is not installed, the contents of the corresponding
locations in main storage remain unchanged.
The word beginning at absolute storage address
268 is reserved for storing additional status as re­
quired by certain model-dependent If no
feature requiring this field is installed, the contents
of the field remain unchanged upon execution of the
store-status function.
The following table lists the fields that are stored,
their length, and their location in main storage.
Length in Absolute
Field Bytes Address
1 CPU timer 8 216
Clock comparator 8 224
Current PSW 8 256 Prefix 4 264
Model-dependent feature 4 268 F-P registers 0-6 32 352
General registers 0-15 64 384
Control registers 0-15 64 448
Explanation:
1 Decimal iEiddress of the first byte of the field in absolute main
storage. Permanently Assigned Storage for Store Status
The contents of the registers are not changed. If
an error is encountered during the operation, the CPU enters the check-stop state.
The store-status operation can be initiated by the
operator on the system console. The operator con­
trols andl the procedure for initiating the function
may differ among models and are described in the System Library (SL) publication for the model. In a
54 Sysh:m/370 Principles of Operation
multiprocessing system, the store-status operation
can also be initiated at the addressed CPU by execu­
ting SIGNAL PROCESSOR, specifying the stop­
and-store-status order.
Initial Program Loading
Initial program loading (IPL) is provided for the
initiation of processing when the contents of main
storage or of the pSW are not suitable for process-
ing.
Initial program loading is initiated manually by
selecting an input device with the load-unit-address
switches and then pressing the load key. Pressing the
load key causes a system-clear or an initial-program­
reset operation to be performed on the CPU, as de­
termined by the setting of the enable-system-clear
key. Subsequently, a read operation is initiated from
the selected input device.
The read operation is performed as if a START I/O instruction were executed that specified the
device addressed by the load-unit-address switches
and used a channel address word ( CAW) containing
a protection key of zero and a channel command
word (CCW) address of 0. The address set up on
the load-unit-address switches provides the 12 low­
order bits of the I/O address; zeros are implied for
the high-order address bits. Although the location of
the first CCW to be executed is specified as 0, the
first CCW actually executed is an implied CCW,
containing, in effect, a read command with the mod­
ifier bits set to zero, a data address of 0, a byte
count of 24, the chain-command flag on, the
suppress-incorrect-Iength-indication flag on, the
chain-data flag off, the skip flag off, and the
program-controlled-interruption (PCI) flag off. The
CCW fetched, as a result of command chaining,
from location 8 or 16, as well as any subsequent
CCW in the IPL sequence, is interpreted the same as
a CCW in any I/O operation, with the exception
that the PCI flag is ignored.
When the I/O device provides channel-end status
for the last operation of the IPL chain and no excep­
tional conditions are detected in the operation, a
new PSW is obtained from locations 0-7. When this PSW specifies the BC mode, the I/O address that
was used for the IPL operation is stored at locations
2 and 3; when the EC mode is specified, the I/O address is stored at locations 186-187, and zeros are
stored at location 185. The load indicator is turned
off, and CPU operation proceeds under the control
of the new PSW. When channel-end status for the IPL operation is
presented, either separate from or along with device­
end status, no I/O interruption condition is generat­
ed. Similarly, any PCI flags specified by the pro-

gram in the CCWs used for the IPL sequence are
ignored. If the device-end status for the IPL opera­
tion is provided separately after channel-end status,
it causes an 110 interruption condition to be generat­
ed. If'the IPL 110 operation or the PSW loading is
not completed satisfactorily, the CPU idles, and the
load indicator remains on. This occurs when the
device designated by the address set up on the load­
unit-address switches is not operational, when the
device or channel signals any condition other than
channel end, device end, or status modifier during or
at the completion of the IPL II 0 operation, or when
the PSW loaded from location 0 has a format error
that is recognized during the loading procedure. The
address of the 110 device used in the IPL operation
is not stored. The contents of locations 0-7 are un­
predictable, but the contents of other main-storage
locations remain unchanged. When less than eight
bytes are read into the doubleword at location 0, the PSW fetched from location 0 at the conclusion of
the IPL operation is unpredictable.
Programming Notes
The information read into locations 8-15 and 16-23
may be used as CCWs for reading additional infor­
mation during the IPL sequence: the CCW at location
8 may specify reading additional CCW s elsewhere in
main storage, and the CCW at location 16 may speci­
fy the transfer-in-channel command, causing trans­
fer to these CCWs.
The status-modifier bit has its normal effect dur­
ing the IPL operation, causing the channel to fetch
and chain to the CCW whose main-storage address
is 16 higher than that of the current CCW. This ap­
plies also to the initial chaining that occurs after
completion of the read operation specified by the
implicit CCW.
The PSW that is loaded at the completion of the IPL procedure may be provided by the first eight
bytes of the IPL 110 operation or may be read into
locations 0-7 by a subsequent CCW.
The IPL 110 operation implicitly specifies the use
of the first 24 bytes of main storage. Since the re­
mainder of the IPL program may be placed in any
part of storage, it is possible to preserve such areas
of storage as the PSW and logout areas, which may
be helpful in recovery.
When the PSW in location 0 has bit 14 set to one,
the CPU is placed in the wait state after the IPL procedure is completed; at that point, the manual
indicator is off, and the wait indicator is on. System Control 55