storage environment, the indirect-data-addressing
facility is provided in the channel.
The address-translation facility requires that the CPU be equipped with the extended-control facility,
as address translation is under control of bit 5 of the
extended-control (EC) PSW. The address-translation facility includes the in­
structions LOAD REAL ADDRESS, RESET REF­
ERENCE BIT, and PURGE TLB. It makes use of
control register 1 and bits 8-12 in control register O. Logical Storage Addressing
Address translation is achieved by treating the ad­
dresses supplied by the program as logical addresses.
When the dynamic-address-translation facility is
active, a logical address is translated during a storage
reference into the corresponding real address, which
designates a location in real storage. When the
dynamic-address-translation facility is not installed
or translation is not specified, a real address is iden­
tical to the corresponding logical address.
In the process of translation, two types of Units of
information are recognized--segments and pages. A
segment is a block of sequential logical addresses
spanning 65,536 (64K) or 1,048,576 (lM) bytes
and beginning at an address that is a multiple of its
size. The size of the segment is controlled by bits 11
and 12 of control register O. A page is a block of
contiguous storage containing 2,048 (2K) or 4,096
(4K) bytes and beginning at an address that is a
multiple of its size. The size of the page is con­
trolled by bits 8 and 9 of control register O. The logical address, accordingly, is divided into a
segment-index field, a page-index field, and a byte­
index field. The size of these fields depends on the
segment and page size.
The segment index starts with bit 8 of the logical
address and extends through bit 15 for a 64K-·byte segment size and through bit 11 for a 1M-byte seg­
ment size. The page index starts with the bit follow­
ing the segment index and extends through bit 19 for
a 4K-byte page size and through bit 20 for a 2K­
byte page size. The byte index comprises the remain­
ing 11 or 12 low-order bits oJ the logical address.
The formats of the logical address are as follows:
For 64K-byte segments and 4K-byte pages: Segment :----1 __ I_nd_e_x ____ __ -L ____ o 8 16 20 31
58 System/370 Principles of Operation
For 64K-byte segments and 2K-byte pages:
o 8
Segment Index I I Byte Index 16 21
For 1M-byte segments and 4K-byte pages: I Page Index I
Byte Index o 8 12 20 For 1M-byte segments and 2K-byte pages:
31
31 I Page Index I Byte Index I o 8 12 21 31
Logical addresses are translated into real address­
es by means of two translation tables, a segment
table and a page table, which reflect the current as­
signment of real storage. The assignment of real
storage occurs in units of pages, the reallocations being assigned contiguously within a page. The
pages need not be adjacent in real storage even
though assigned to a set of sequential logical address­
es.
Control
Address translation is controlled by the translation­
mode bit in the PSW and by a set of bits in control
registers 0 and 1. Additional controls are located in
the translation tables.
PSW
When the dynamic-address-translation facility is
installed, the CPU can operate either in the transla­
tion mode or without address translation. The mode
of operation is controlled by bit 5 of the extended­
control PSW, the translation-mode bit. When this
bit is one, translation is specified; when this bit is
zero, no implicit dynamic address translation takes
place, and logical addresses are used as real address­
es.
Control Register 0
Four bits are provided in control register 0 for the
control of page size and segment size, as follows:
8 10 12

The bits are defined as follows:
Page Size (PS): Bits 8 and 9 of control register 0 control the size of pages, using the following code:
Bits 8 and 9
of Control Register 0 01 10 Page Size (Bytes)
2,048 (2K)
4,096 (4K)
When bit positions 8 and 9 contain a binary code
other than 01 or 10, a translation-specification ex­
ception is recognized as part of the execution of an
instruction using address translation, and the opera­
tion is suppressed. These bits are initialized to zeros.
Segment Size (SS): Bits 11 and 12 of control regis­
ter 0 control the size of segments, using the follow­
ing code:
Bits 11 and 12
of Control Register 0 00 10 Segment Size (Bytes)
65,536 (64K)
1,048,576 (1M)
When bit position 12 contains a one, a translation­
specification exception is recognized as part of the
execution of an instruction using address translation,
and the operation is suppressed. These bits are ini­
tialized to zeros.
Bit 10 of control register 0 must be zero when an
instruction is executed that uses address translation;
otherwise, a translation-specification exception is
recognized as part of the execution of the instruc­
tion, and the operation is suppressed. The bit is not
checked for zero when address translation is not
installed.
Control Register 1
Bits 0-25 of control register 1 designate the begin­
ning and length of the segment table:
Length I Segment-Table Addr.ss
o 8 26 31
The fields in the register are allocated as follows:
Segment-Table Length: Bits 0-7 of control register 1
designate the length of the segment table in units of
64 bytes, thus making the length of the segment
table variable in multiples of 16 entries. The length
of the segment table, in units of 64 bytes, is equal to
one more than the value in bit positions 0-7. The
contents of the length field are used to establish
whether the entry designated by the segment-index
portion of the logical address falls within the seg­
ment table. Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
Segment-Table Address: Bits 8-25 of control register 1,
with six low-order zeros appended, form a 24-bit
real address that designates the beginning of the
segment table.
Programming Note
The validity of the information loaded into a control
register, including that pertaining to dynamic address
translation, is not checked at the time the register is
loaded. This information is checked and the pro­
gram exception, if any, is indicated at the time the
inf ormation is used.
The information pertaining to dynamic address
translation is considered to be used when an instruc­
tion is executed in the translation mode or when LOAD REAL ADDRESS is executed. The informa­
tion is not considered to be used when the PSW specifies translation, but an I/O, external, restart, or
machine-check interruption occurs before an instruc­
tion is executed, including the case when the PSW specifies the wait state.
Translation Tables
Two types of translation tables are used for the
translation process-a segment table and a page
table. These tables reside in main storage.
Segment-Table Entries
The entry fetched from the segment table designates
the length, availability, and origin of the correspond­
ing page table.
An entry in the segment table has the following
format: Page-Table Address
o 4 8 29 31
The fields in the segment-table entry are allocated
as follows:
Page-Table Length: Bits 0-3 designate the length of
the page table in increments that are equal to a six­
teenth of the maximum size of the table, the maxi­
mum size depending on the size of segments and
pages. The length of the page table, in units one­
sixteenth of the maximum size, is equal to one more
than the value in bit positions 0-3. The length field is
compared against the high-order four bits of the
page-index portion of the logical address to deter­
mine whether the page index designates an entry
within the page table.
Dynamic Address Translation 59