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By TNL: GN22-0498
different logical page the use of the Gommon reallocation is not necessarily recog­
nized.
When the use of a common real storage location
is not recognized, storing into the location does not
necess.arily appear to be completed by the time the instruetion or operand is fetched from the location.
In the case of unrecognized operand overlap, the
portion of the instruction definition pertaining to
overlap does not necessarily apply.
Any change to the key in storage appears to be
completed before the following reference to the as­
sociated storage block is made, regardless of whether
the reference to the storage location is made by a
logical or real address. Analogously, any prior refer­
ences to the storage block appear completed when
the key for that block is changed or inspected. Sinee the interlocks discussed in this section peI:­ tain to references made by the same CPU, a com­
mon reallocation implies also a common absolute
location. This is true because, for anyone CPU, a
one-to-one correspondence exists between real and
absolute addresses, and a change in the prefix value,
changing this mapping, causes serialization. interlocks between storage referenees are
summarized in the table "Summary of Interlocks
Between Storage References."
Table Manipulation
Translation-Lookaside Buffer
To enhance performance, the dynamic-address­
translation mechanism normally is implemented such
that some of the information specified in the seg-
ment and page tables is maintained in a special buff­
er, referred to as the translation-Iookaside buffer
(TLB). The CPU necessarily refers to a table entry
in main storage only for the initial access to that
entry. This information subsequently may be main­
tained in the TLB, and all subsequent translations
involving translation-table entries from the same real
storage location may be performed using the info:r­
mation recorded in the TLB. The presence of the TLB
affects the translation process to the extent that a
modification of the contents of a table entry in main
storage does not necessarily have an immediate ef­
fect' if any, on the translation.
The size and the structure of the TLB depends on
the model. For instance, the TLB may be imple­
mented such as to contain only a few entries pertain­
ing to the currently designated segment table, each
entry consisting of the high-order portions of a logi­
cal address and its corresponding real address; or it
may contain arrays of values where the real page
address is selected on the basis of the current
segment-table starting address, page-size designa­
tion, segment-size designation, and the high-order
bits of the logical address. Entries within the TLB
are not explicitly addressable by the program.
The following sections describe the conditions
under which information may be placed in the TLB
and information from the TLB may be used for ad­
dress translation, and describe how changes to the
translation tables affect the translation process. In­
formation is not necessarily retained ih the TLB
under all conditions for which such retention is per­
missible. Furthermore, information in the TLB may I nterlolcks between two references by a single CPU to a location in real storage when the same real location is designated by different addresses. Is it necessarily recognized that reference is made to the same real location? Addresses used to designate a location in real storage Real X and Real X Real X and Logical A Logical A and Logical A Logical A and Logical B Explanation: Not applicable. References within
Same Instruction Operand-Operand
Yes
Yes
No
References by Two Instructions Operand-Operand Operand-I nstruction
Yes Yes
Yes Yes
Yes Yes
Yes No*
* Real X Logical A Logical B
Reference to the same real location is recognized when a serialization function occurs between the two references.
A real address designating location X in real storage.
A logical address A designating location X in real storage.
A logical address B deSignating location X in real storage. Summary of Interlocks Between Storage References
64 System/370 Principles of Operation

be purged under conditions additional to those for
which purging is mandatory.
States of Translation-Table Entries
The effects of any manipulation of the contents of a
table entry by the program and the recording of its
contents in the TLB depend on whether the entry is
valid, on whether the entry is attached, and on
whether the entry is active.
The valid state denotes that the segment or page
associated with the table entry is available. An entry
is valid when the segment-invalid bit or page-invalid
bit in the entry is zero. A segment-translation or
page-translation exception is recognized when an at­
tempt is made to use an invalid table entry for trans­
lation.
The attached state denotes that the CPU can
attempt to use the table entry for implicit address
translation and hence depends on the state of the
CPU as specified by the PSW, control register 1, and
bit positions 8-12 of control register o.
A segment-table entry is attached to a CPU when
all of the following three conditions are met: • The current PSW specifies the translation mode. • The entry is within the segment table designated
by control register 1. • With the segment size currently specified in
control register 0, the entry can be designated
by a logical address.
The PSW is considered to specify the translation
mode when bit 5 is one and the EC mode is speci­
fied, regardless of whether the contents of any other
PSW fields are due to cause an exception to be rec­
ognized.
A page-table entry is attached to a CPU when it
is within the page table designated by the page-table
address and page-table length either in an attached
and valid segment-table entry or in a TLB copy of
an attached segment-table entry and by the page­
size specification in control register O. The active state denotes that the table entry may
remain recorded in the TLB.
A table entry becomes active when it is made
both valid and attached or after the TLB is purged
with the table entry both valid and attached. A table
entry ceases being active when the TLB is purged.
Although all entries become inactive during a purge
of the TLB, entries that are both valid and attached
become active at the completion of the purge. The segment size controls how many segment-table
entries can be referred to for translation. Both the
page size and segment size control selection of page-
Page of GA22-7000-4 Revised September 1, 1975
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table entries and hence may affect whether or not an
entry is attached.
Although a table entry becomes active when it is
made both valid and attached, it need not remain
valid and attached to remain active. For example, an
attached table entry remains active when the I bit is
set to one, and a valid table entry remains active
when it is made unattached.
Use of the Translation-Lookaside Buffer
A segment-table entry or a page-table entry may be
placed in the TLB only when the entry is attached
and the I bit in the entry is zero. The entry may be
placed in the TLB as soon as it becomes attached
and valid.
Information from a TLB copy of a segment-table
entry may be used for implicit address translation
only when the TLB entry was formed using informa­
tion that was fetched from storage as an attached
and valid segment-table entry, only when that real
storage location is selected as a segment-table entry
during the translation process, and only when the
table entry is attached at the time of the selection.
Information from a TLB copy of a page-table
entry may be used for implicit address translation
only when the TLB entry was formed using informa­
tion that was fetched from storage as an attached
and valid page-table entry, only when that real stor­
age location is selected as a page-table entry during
the translation process and the table entry is attached
at the time of selection, and only when the
page size at the time of forming the TLB copy was
the same as the current page size.
The operand address of LOAD REAL AD­
DRESS is translated without the use of the TLB
contents. Translation in this case is performed by the
use of the designated tables in main storage.
All information in the TLB is necessarily cleared
only by execution of PURGE TLB, SET PREFIX,
or CPU reset.
Programming No entries can be placed in the TLB in the BC mode
or when translation is not specified, because the
table entries at this time are not attached. In particu­
lar, translation of the operand address of LOAD REAL ADDRESS, with translation suppressed, does
not cause entries to be placed in the TLB.
Conversely, when translation is specified, infor­
mation may be loaded into the TLB from all
translation-table entries that could be used for ad­
dress translation, given the current designation of
page size, segment size, segment-table address, and
segment-table length. The loading of the TLB does
not depend on whether the entry is used for transla-
Dynamic Address Translation 65