Exponent-Underflow Exception
An exponent-underflow exception is recognized
when the result characteristic in floating-point addi
tion, subtraction, multiplication, halving, or division
is less than zero and the result fraction is not zero.
The interruption may be disallowed in the BC
mode byPSW bit 38, and in the EC mode by PSW bit 22.
The operation is completed. The setting of the
exponent-underflow mask also affects the result of
the operation. When the mask bit is zero, the sign,
characteristic, and fraction are set to zero, making
the result a true zero. When the mask bit is one, the
fraction is normalized, the characteristic is made 128
larger than the correct characteristic, and the sign
and fraction remain correct.
The instruction-length code is 1 or 2.
Significance Exception
A significance exception is recognized when the
result fraction in floating-point addition or subtrac
tion is zero.
The interruption may be disallowed in the BC
mode byPSW bit 39, and in the EC mode by PSW bit 23.
The operation is completed. The significance
mask affects also the result of the operation. When
the mask bit is zero, the operation is completed by
replacing the result with a true zero. When the mask
bit is one, the operation is completed without further
change to the characteristic and sign of the result.
The instruction-length code is 1 or 2.
Floating-Point-Divide Exception
A floating-point-divide exception is recognized when
a floating-point division by a number with a zero
fraction is attempted.
The operation is suppressed.
The instruction-length code is 1 or 2.
Segment-Translation Exception
A exception is recognized when:
1. The segment-table entry is outside the segment
table.
2. The segment-invalid bit has the value 1.
The exception is recognized as part of the execu
tion of the instruction that needs the segment-table
entry in the translation of either the instruction or
operand address, except for the operand address inLOAD REAL ADDRESS, in which case the condi
tion is indicated by the setting of the condition code.
The unit of operation is nullified.
The segment and page portion of the logical ad
dress causing the exception is placed in main storage
at locations 145-147, and zeros are placed at loca-
tion 144. When 2,048-byte pages are used, the low
order 11 bits of the address are unpredictable; when
4,096-byte pages are used, the low-order 12 bits of
the address are unpredictable.
When the exception occurs during a reference to
an operand location, the instruction-length code
OLC) is 1, 2, or 3 and indicates the length of the
instruction causing the exception. When the excep
tion occurs during fetching of an instruction, the ILC
is 1, 2, or 3, the indication being unpredictable.
Page-Translation Exception
A page-translation exception is recognized when:
1. The page-table entry is outside the page table.
2. The page-invalid bit has the value 1.
The exception is recognized as part of the execu
tion of the instruction that needs the page-table en
try in the translation of either the instruction or oper
and address, except for the operand address inLOAD REAL ADDRESS, in which case the condi
tion is indicated by the setting of the condition code.
The unit of operation is nullified.
The segment and page portion of the logical ad
dress causing the exception is placed in main storage
at locations 145-147, and zeros are placed at loca
tion 144. When 2,048-byte pages are used, the low
order 11 bits of the address are unpredictable; when
4,096-byte pages are used, the low-order 12 bits of
the address are unpredictable.
When the exception occurs during a reference to
an operand location, the instruction-length code
OLC) is 1, 2, or 3 and indicates the length of the
instruction causing the exception. When the excep
tion occurs during fetching of an instruction, the ILC
is 1, 2, or 3, the indication being unpredictable.
Translation-Specification Exception
A translation-specification exception is recognized
when:
1. Bit positions 8 and 9 of control register0 con- tain values 00 or 11.
2. Bit position10 of control register 0 contains a
one.
3. Bit positions 11 and 12 of control register0 contain values 01 or 11.
4.
Bit positions 4-7 or29-30 in a valid segment
table entry do not contain zeros (on some
models these bit positions are not checked for
zeros).
5. Depending on the page size, the one or two bit
positions next to the low-order bit in a valid
page-table entry do not contain zeros.
The exception is recognized only as part of the
execution of an instruction using address translation,
Interruptions 79
An exponent-underflow exception is recognized
when the result characteristic in floating-point addi
tion, subtraction, multiplication, halving, or division
is less than zero and the result fraction is not zero.
The interruption may be disallowed in the BC
mode by
The operation is completed. The setting of the
exponent-underflow mask also affects the result of
the operation. When the mask bit is zero, the sign,
characteristic, and fraction are set to zero, making
the result a true zero. When the mask bit is one, the
fraction is normalized, the characteristic is made 128
larger than the correct characteristic, and the sign
and fraction remain correct.
The instruction-length code is 1 or 2.
Significance Exception
A significance exception is recognized when the
result fraction in floating-point addition or subtrac
tion is zero.
The interruption may be disallowed in the BC
mode by
The operation is completed. The significance
mask affects also the result of the operation. When
the mask bit is zero, the operation is completed by
replacing the result with a true zero. When the mask
bit is one, the operation is completed without further
change to the characteristic and sign of the result.
The instruction-length code is 1 or 2.
Floating-Point-Divide Exception
A floating-point-divide exception is recognized when
a floating-point division by a number with a zero
fraction is attempted.
The operation is suppressed.
The instruction-length code is 1 or 2.
Segment-Translation Exception
A exception is recognized when:
1. The segment-table entry is outside the segment
table.
2. The segment-invalid bit has the value 1.
The exception is recognized as part of the execu
tion of the instruction that needs the segment-table
entry in the translation of either the instruction or
operand address, except for the operand address in
tion is indicated by the setting of the condition code.
The unit of operation is nullified.
The segment and page portion of the logical ad
dress causing the exception is placed in main storage
at locations 145-147, and zeros are placed at loca-
tion 144. When 2,048-byte pages are used, the low
order 11 bits of the address are unpredictable; when
4,096-byte pages are used, the low-order 12 bits of
the address are unpredictable.
When the exception occurs during a reference to
an operand location, the instruction-length code
OLC) is 1, 2, or 3 and indicates the length of the
instruction causing the exception. When the excep
tion occurs during fetching of an instruction, the ILC
is 1, 2, or 3, the indication being unpredictable.
Page-Translation Exception
A page-translation exception is recognized when:
1. The page-table entry is outside the page table.
2. The page-invalid bit has the value 1.
The exception is recognized as part of the execu
tion of the instruction that needs the page-table en
try in the translation of either the instruction or oper
and address, except for the operand address in
tion is indicated by the setting of the condition code.
The unit of operation is nullified.
The segment and page portion of the logical ad
dress causing the exception is placed in main storage
at locations 145-147, and zeros are placed at loca
tion 144. When 2,048-byte pages are used, the low
order 11 bits of the address are unpredictable; when
4,096-byte pages are used, the low-order 12 bits of
the address are unpredictable.
When the exception occurs during a reference to
an operand location, the instruction-length code
OLC) is 1, 2, or 3 and indicates the length of the
instruction causing the exception. When the excep
tion occurs during fetching of an instruction, the ILC
is 1, 2, or 3, the indication being unpredictable.
Translation-Specification Exception
A translation-specification exception is recognized
when:
1. Bit positions 8 and 9 of control register
2. Bit position
one.
3. Bit positions 11 and 12 of control register
4.
Bit positions 4-7 or
table entry do not contain zeros (on some
models these bit positions are not checked for
zeros).
5. Depending on the page size, the one or two bit
positions next to the low-order bit in a valid
page-table entry do not contain zeros.
The exception is recognized only as part of the
execution of an instruction using address translation,
Interruptions 79