Exponent-Underflow Exception
An exponent-underflow exception is recognized
when the result characteristic in floating-point addi­
tion, subtraction, multiplication, halving, or division
is less than zero and the result fraction is not zero.
The interruption may be disallowed in the BC
mode by PSW bit 38, and in the EC mode by PSW bit 22.
The operation is completed. The setting of the
exponent-underflow mask also affects the result of
the operation. When the mask bit is zero, the sign,
characteristic, and fraction are set to zero, making
the result a true zero. When the mask bit is one, the
fraction is normalized, the characteristic is made 128
larger than the correct characteristic, and the sign
and fraction remain correct.
The instruction-length code is 1 or 2.
Significance Exception
A significance exception is recognized when the
result fraction in floating-point addition or subtrac­
tion is zero.
The interruption may be disallowed in the BC
mode by PSW bit 39, and in the EC mode by PSW bit 23.
The operation is completed. The significance
mask affects also the result of the operation. When
the mask bit is zero, the operation is completed by
replacing the result with a true zero. When the mask
bit is one, the operation is completed without further
change to the characteristic and sign of the result.
The instruction-length code is 1 or 2.
Floating-Point-Divide Exception
A floating-point-divide exception is recognized when
a floating-point division by a number with a zero
fraction is attempted.
The operation is suppressed.
The instruction-length code is 1 or 2.
Segment-Translation Exception
A exception is recognized when:
1. The segment-table entry is outside the segment
table.
2. The segment-invalid bit has the value 1.
The exception is recognized as part of the execu­
tion of the instruction that needs the segment-table
entry in the translation of either the instruction or
operand address, except for the operand address in LOAD REAL ADDRESS, in which case the condi­
tion is indicated by the setting of the condition code.
The unit of operation is nullified.
The segment and page portion of the logical ad­
dress causing the exception is placed in main storage
at locations 145-147, and zeros are placed at loca-
tion 144. When 2,048-byte pages are used, the low­
order 11 bits of the address are unpredictable; when
4,096-byte pages are used, the low-order 12 bits of
the address are unpredictable.
When the exception occurs during a reference to
an operand location, the instruction-length code
OLC) is 1, 2, or 3 and indicates the length of the
instruction causing the exception. When the excep­
tion occurs during fetching of an instruction, the ILC
is 1, 2, or 3, the indication being unpredictable.
Page-Translation Exception
A page-translation exception is recognized when:
1. The page-table entry is outside the page table.
2. The page-invalid bit has the value 1.
The exception is recognized as part of the execu­
tion of the instruction that needs the page-table en­
try in the translation of either the instruction or oper­
and address, except for the operand address in LOAD REAL ADDRESS, in which case the condi­
tion is indicated by the setting of the condition code.
The unit of operation is nullified.
The segment and page portion of the logical ad­
dress causing the exception is placed in main storage
at locations 145-147, and zeros are placed at loca­
tion 144. When 2,048-byte pages are used, the low­
order 11 bits of the address are unpredictable; when
4,096-byte pages are used, the low-order 12 bits of
the address are unpredictable.
When the exception occurs during a reference to
an operand location, the instruction-length code
OLC) is 1, 2, or 3 and indicates the length of the
instruction causing the exception. When the excep­
tion occurs during fetching of an instruction, the ILC
is 1, 2, or 3, the indication being unpredictable.
Translation-Specification Exception
A translation-specification exception is recognized
when:
1. Bit positions 8 and 9 of control register 0 con-­ tain values 00 or 11.
2. Bit position 10 of control register 0 contains a
one.
3. Bit positions 11 and 12 of control register 0 contain values 01 or 11.
4.
Bit positions 4-7 or 29-30 in a valid segment­
table entry do not contain zeros (on some
models these bit positions are not checked for
zeros).
5. Depending on the page size, the one or two bit
positions next to the low-order bit in a valid
page-table entry do not contain zeros.
The exception is recognized only as part of the
execution of an instruction using address translation,
Interruptions 79
that is, when an instruction is executed with bit 5 of
the EC-·mode PSW one or when LOAD REAL AD­
DRESS is executed. Causes 1-3 are recognized on
any translation attempt; causes 4 and 5 are recog­
nized only for table entries that are actually used.
The unit of operation is suppressed.
When the exception occurs during a reference to
an operand location, the instruction-length code OLC) is 1, 2, or 3 and indicates the length of the
instruction causing the exception. When the excep­
tion occurs during fetching of an instruction, the ILC
is 1, 2, or 3, indicating the number of halfword loca­
tions by which the instruction address has been up­
dated. It is unpredictable whether the code is 1, 2, or
3.
Programming Note
When a translation-specification exception is recog­
nized in the process of translating an instruction
address, the operation is suppressed. In this ease, the
instruction-length code OLC) is needed to derive the
address of the instruction, as the instruction address
in the old PSW has been incremented by the amount
specified by the ILC. In the case of segment·· translation and page-translation exceptions, the op­
eration is nullified, the instruction address in the old
PSW identifies the instruction, and the ILC is redun­
dant. Special-Operation Exception
A special-operation exception is recognized when a
SET SYSTEM MASK instruction is encountered in
the supervisor state and the SSM-control bit, bit 1 of
control register 0, is one.
The execution of SET SYSTEM MASK is sup­
pressed.
The instruction-length code is 2.
Monitor Event
A monitor event is recognized when MONITOR CALL is: executed and the mask bit in control regis­
ter 8 corresponding to the class specified by instruc­
tion bits 12-15 is one.
The operation is completed.
As part of the interruption, information identify­
ing the event is placed in main storage at locations
148-149 and 156-159. See "Monitoring" in the
chapter "System Control" for a detailed description
of the inlterruption condition.
The instruction-length code IS 2.
Program Event
A program event is recognized when program-event
recording is specified by the contents of control reg­
isters 9-11 and one or more of these events occur. 80 System/370 Principles of Operation
In the EC mode, the interruption may be disal­
lowed by PSW bit 1. In the BC mode, program­
event recording is disabled.
The unit of operation is completed, unless another
concurrently indicated condition has caused the unit
of operation to be nullified, suppressed, or terminat­
ed.
As part of the interruption, information identify­
ing the event is placed in main storage at locations
150-155. See "Program-Event Recording" in the
chapter "System Control" for a detailed description
of the interruption condition.
The instruction-length code is 0, 1,2, or 3. Code
o can be set only because of a protection addressing
or specification condition that is concurrently indi­
cated.
Recognition of Access Exceptions
The protection, addressing, segment-translation,
page-translation, and translation-specification excep­
tions are collectively referred to as access excep­
tions. The table "Handling of Access Exceptions"
summarizes the conditions that can cause these ex­
ceptions and the action taken when they are encoun­
tered.
An access exception due to fetching an instruction
is indicated when an instruction halfword cannot be
fetched without encountering the exception. The
exception is indicated as part of the execution of the
instruction.
Except for the specific cases described below, an
access exception due to a reference to an operand
location is indicated whenever a reference to a part
of the designated storage operand causes the excep­
tion. The exception for a partially inaccessible oper­
and is recognized even if the operation could be
completed without the use of the inaccessible part of
the operand. The access exception is indicated as
part of the execution of the instruction making the
reference.
Whenever an access to an operand location can
cause an access exception to be recognized, the word "access" is included in the list of program exceptions
in the description of the instruction. This entry also
indicates which operand can cause the exception to
be recognized and whether the exception is recog­
nized on a fetch or store access to that operand loca­
tion. Additionally, each instruction can cause an
access exception to be recognized due to instruction
fetch.
The following are exceptions or special cases
where the instruction does not explicitly specify the
extent of the storage operand or where the instruc­
tion provides for completion of execution without
the use of the entire operand. The handling of these
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