1. Translation-specification exception due to invalid page size or segment size
designation or due to a one in bit position 10 of control register O. 2. Se'gment-translation exception due to segment-table entry being outside table.
3. Addressing exception due to segment-table entry being outside main storage of
in:stallation.
4. SElgment-translation exception due to I bit having the value one.
5. Translation-specification exception due to invalid ones in segment-table entry.
6. exception due to page-table entry being outside table.
7. Addressing exception due to page-table entry being outside main storage of
installation.
8. Pclge-translation exception due to I bit having the value one.
9. Tlranslation-specification exception due to invalid ones in page-table entry. 10. Addressing exception due to instruction or operand location outside main
storage of installation.
11. Pmtection exception due to attempt to access a protected instruction.or operand location. The acc:ess exceptions are listed in the order of descending priorities.
Priorities of Access Exceptions
exclusive, and it is unpredictable which is indicated
when both occur. The second instruction halfword is accessed only
if bits 0-1 of the instruction are not 00. The third instruction half word is accessed only if bits 0-1 of
the instruction are 11.
Supervisor-Call Interruption
The supervisor-call interruption occurs as a result of
the execution of the instruction SUPERVISOR CALL. The CPU cannot be disabled for the inter­
ruption, and the interruption occurs immediately
upon the execution of the instruction.
The supervisor-call interruption causes the old PSW to be stored at location 32 and a new PSW to
be fet.ched from location 96.
The contents of bit positions 8-15 of SUPERVI­ SOR CALL are placed in the low-order byte of the
interruption code. The high-order byte of the inter­
ruption code is set to zero. The instruction-length
code is 1, unless the instruction was executed by
means of EXECUTE, in which case the code is 2.
When the old PSW specifies the BC mode, the
interruption code and instruction-length code appear
in the old PSW; when the old PSW specifies the EC
mode, the interruption code is placed at locations
138-Jl39, the instruction-length code is placed in bit
positions 5 and 6 of the byte at location 137, with
84 System/370 Principles of Operation
the other bits set to zero, and zeros are stored at
location 136.
Programming Note
The name "supervisor call" indicates that one of the
major purposes of the interruption is the switching
from problem to supervisor state. This major pur­
pose does not preclude the use of this interruption
for other types of status switching.
The interruption code may be used to convey a
message from the calling program to the supervisor.
External Interruption
The external interruption provides a means by which
the CPU responds to various signals originating ei­
ther from within or from outside of the system.
An external interruption causes the old PSW to be
stored at location 24 and a new PSW to be fetched
from location 88.
The source of the interruption is identified in the
interruption code. When the old PSW specifies the
BC mode, the interruption code is placed in bit posi­
tions 16-31 of the old PSW, and the instruction­
length code is unpredictable. When the old PSW specifies the EC mode, the interruption code is
placed at locations 134-135.
Additionally, in both the BC and EC modes, for
some conditions a 16-bit processor address is associ-

1.A Delayed addressing exception due to an attempted store by a previous instruction (zero I LC). 1.B Delayed protection exception due to an attempted store by a previous instruction (zero I LC). 2. Specification exception due to any PSW error of the type that causes an immediate interruption.
1
3. Specification exception due to an odd instruction address in the PSW.
4. Access exceptions for first instruction halfword.
2
5.A Access exception for second instruction halfword.
2
5.B Access exception for third instruction halfword. 5.C.1 Operation exception. 5.C.2 Privileged-operation exception. 5.C.3 Execute exception. 5.C.4 Special-operation exception.
5.D Specification exception, due to conditions other than those included in 2 and 3 above, for an
instruction that is not installed but has an operation code assigned.
6.A Specification exception due to conditions other than those included in 2, 3, and 5.D above.
2
6.B-.G* Access exceptions for any particular access to an operand in main storage.
3
6.H Data exception.
4 6.1 Decimal-divide exception.
4
7.-14. Fixed-point divide, floating-point divide, and conditions, other than program events, which result in completion. These conditions are mutually exclusive.
Explanation:
Numbers indicate priority, with priority decreasing in ascending order of numbers; letters indicate no priority.
* As in instruction fetching, separate accesses may occur for
each portion of an operand. Each of these accesses is of equal priority, and in effect a different letter is assigned to
each. There is a maximum of six different operand access
exceptions corresponding to fetch accesses to two operands,
each of which crosses a protection or page boundary, and
store accesses to one operand which crosses a boundary.
Access exceptions for INSERT STORAGE KEY, SET STORAGE KEY, RESET REFERENCE BIT, and LOAD REAL ADDRESS are also included in 6.B.
PSW errors which cause an immediate interruption may
be introduced by a new PSW loaded as a result of an
interruption or by the instructions LPSW, SSM, and STOSM. The priority shown in the chart is that for the case of an
error introduced by an interruption and may also be
considered as the priority for the case of an error introduced
by the previous instruction. The error is introduced only if
the instruction encounters no other exceptions. If the
recognition of this exception is considered to be part of the
execution of the instruction introducing the error, then it
is of lower priority than all other exceptions for that instruction.
Priorities of Program Interruption Conditions
ated with the source of the interruption and is stored
at locations 132-133. When the processor address is
stored, bit 6 of the interruption code is set to one.
When bit 6 is zero and the old PSW specifies the BC
mode, the contents of locations 132-133 remain
unchanged. When bit 6 is zero and the old PSW 2 In the case of an EXECUTE instruction, both EXECUTE and the subject instruction of the EXECUTE must be
accessed and interpreted. In this case, the priorities shown
are for the subject instruction. The priority of exceptions
associated with the EXECUTE can be considered as being
prefixed with a "3.", thus occurring between priorities 3
and 4, and numbered as follows: 3.4, 3.5.A, and 3.6.A.
3 For MOVE LONG and COMPARE LOGICAL LONG, an
access exception for a particular operand can be indicated only if the R field for that operand designates an even­
numbered register. For instructions requiring that storage
operands be specified on integral boundaries, an access
exception may be indicated for the extent of the operand
that would be implied if the byte-oriented operand feature applied. 4 The exception can be indicated only if the sign, digit, or
digits responsible for the exception were fetched without
encountering an access exception.
specifies the EC mode, zeros are stored at locations
132-133.
An external interruption for a particular source
can occur only when the CPU is enabled for inter­
ruption by that source. Whether the CPU is enabled
for external interruption is controlled by the external
Interruptions 85