1.A Delayed addressing exception due to an attempted store by a previous instruction (zero I LC). 1.B Delayed protection exception due to an attempted store by a previous instruction (zero I LC). 2. Specification exception due to any PSW error of the type that causes an immediate interruption.
1
3. Specification exception due to an odd instruction address in the PSW.
4. Access exceptions for first instruction halfword.
2
5.A Access exception for second instruction halfword.
2
5.B Access exception for third instruction halfword. 5.C.1 Operation exception. 5.C.2 Privileged-operation exception. 5.C.3 Execute exception. 5.C.4 Special-operation exception.
5.D Specification exception, due to conditions other than those included in 2 and 3 above, for an
instruction that is not installed but has an operation code assigned.
6.A Specification exception due to conditions other than those included in 2, 3, and 5.D above.
2
6.B-.G* Access exceptions for any particular access to an operand in main storage.
3
6.H Data exception.
4 6.1 Decimal-divide exception.
4
7.-14. Fixed-point divide, floating-point divide, and conditions, other than program events, which result in completion. These conditions are mutually exclusive.
Explanation:
Numbers indicate priority, with priority decreasing in ascending order of numbers; letters indicate no priority.
* As in instruction fetching, separate accesses may occur for
each portion of an operand. Each of these accesses is of equal priority, and in effect a different letter is assigned to
each. There is a maximum of six different operand access
exceptions corresponding to fetch accesses to two operands,
each of which crosses a protection or page boundary, and
store accesses to one operand which crosses a boundary.
Access exceptions for INSERT STORAGE KEY, SET STORAGE KEY, RESET REFERENCE BIT, and LOAD REAL ADDRESS are also included in 6.B.
PSW errors which cause an immediate interruption may
be introduced by a new PSW loaded as a result of an
interruption or by the instructions LPSW, SSM, and STOSM. The priority shown in the chart is that for the case of an
error introduced by an interruption and may also be
considered as the priority for the case of an error introduced
by the previous instruction. The error is introduced only if
the instruction encounters no other exceptions. If the
recognition of this exception is considered to be part of the
execution of the instruction introducing the error, then it
is of lower priority than all other exceptions for that instruction.
Priorities of Program Interruption Conditions
ated with the source of the interruption and is stored
at locations 132-133. When the processor address is
stored, bit 6 of the interruption code is set to one.
When bit 6 is zero and the old PSW specifies the BC
mode, the contents of locations 132-133 remain
unchanged. When bit 6 is zero and the old PSW 2 In the case of an EXECUTE instruction, both EXECUTE and the subject instruction of the EXECUTE must be
accessed and interpreted. In this case, the priorities shown
are for the subject instruction. The priority of exceptions
associated with the EXECUTE can be considered as being
prefixed with a "3.", thus occurring between priorities 3
and 4, and numbered as follows: 3.4, 3.5.A, and 3.6.A.
3 For MOVE LONG and COMPARE LOGICAL LONG, an
access exception for a particular operand can be indicated only if the R field for that operand designates an even­
numbered register. For instructions requiring that storage
operands be specified on integral boundaries, an access
exception may be indicated for the extent of the operand
that would be implied if the byte-oriented operand feature applied. 4 The exception can be indicated only if the sign, digit, or
digits responsible for the exception were fetched without
encountering an access exception.
specifies the EC mode, zeros are stored at locations
132-133.
An external interruption for a particular source
can occur only when the CPU is enabled for inter­
ruption by that source. Whether the CPU is enabled
for external interruption is controlled by the external
Interruptions 85

mask, ]PSW bit 7, and external submask bits in con­
trol register O. Each source for an external interrup­
tion is assigned a submask bit, and the source can
cause an interruption only when the external-mask
bit is one and the corresponding sub mask bit is one.
The use of the submask bits does not depend on whether the CPU is in the BC or EC mode. the CPU becomes enabled for a pending
external-interruption condition, the interruption
occurs at the completion of the instruction execution
or interruption that causes the enabling.
More than one source may present a request for
an external interruption at the same time. When the CPU becomes enabled for more than one concur­
rently pending request, the interruption occurs for
the pending condition or conditions having the high­
est priority.
The highest priority is assigned to the set of con­
ditions that includes the interval timer, interrupt key,
and external signals 2 through 7. Within this set, all
pending requests for which the CPU is enabled are
indicated concurrently in the interruption code. Next
in priority are interruption requests for the following
sources, the sources being listed in descending order
of priollity: Malfunction alert
Emergency signal
External call
Time-of -day clock sync check
Clock comparator CPU timer
When more than one emergency-signal or
malfunction-alert request exists at a time, the request
associated with the smallest processor address is
honored first. Only one occurrence each of these
conditions can be indicated at a time in the external­
interruption code.
Interval[ Timer
An interruption request for the interval timer is gen­
erated when the value of the interval timer is decre­
mented from a positive number, including zero, to a
negative number. The request is preserved and re­
mains pending in the CPU until it is cleared. The
pending request is cleared when it causes an inter­
ruption and by CPU reset.
The condition is indicated by setting bit 8 in the
interruption code to one and by setting bits 0-7 to
zero. Bits 9-15 are zero unless set to one for another
condition that is concurrently indicated. In the EC
mode, zeros are stored at locations 132-133.
The su bmask bit is located in bit position 24 of
control register O. This bit is initialized to one.
86 System/370 Principles of Operation
Interrupt Key
An interruption request for the interrupt key is gen­
erated when the interrupt key on the operator sec­
tion of the system control panel is activated. The
request is preserved and remains pending in the CPU until it is cleared. The pending request is cleared
when it causes an interruption and by CPU reset.
The condition is indicated by setting bit 9 in the
interruption code to one and by setting bits 0-7 to
zero. Bits 8 and 10-15 are zero unless set to one for
another condition that is concurrently indicated. In
the EC mode, zeros are stored at locations 132-133.
The submask bit is located in bit position 25 of
control register O. This bit is initialized to one.
External Signal
An interruption request for an external signal is gen­
erated when a signal is received on one or more of
the signal-in lines. Up to six signal-in lines may be
connected, providing for external signal 2 through
external signal 7. The request is preserved and re­
mains pending in the CPU until it is cleared. The
pending request is cleared when it causes an inter­
ruption and by CPU reset.
External signals 2 through 7 are indicated by set­
ting to one interruption code bits 10-15, respective­
ly. Bits 0-7 are set to zero, and any other bits in the
low-order byte are made zero unless set to one for
another condition that is concurrently indicated. In
the EC mode, zeros are stored at locations 132-133.
All external signals are subject to control by the
submask bit in bit position 26 of control register O. This bit is initialized to one.
The facility to accept external signals is part of
the direct-control feature. On some models, it is also
available as a separate feature.
Programming Note
The pattern presented in bit positions 10-15 of the
interruption code depends on the pattern received
before the interruption is taken. Because of circuit
skew, all simultaneously generated external signals
do not necessarily arrive at the same time, and some
may not be included in the external interruption
resulting from the earliest signals. These late signals
may cause another interruption to be taken.
Malfunction Alert
An interruption request for malfunction alert is gen­
erated when another CPU that is configured to the CPU enters the check-stop state or loses power. The
request is preserved and remains pending in the re­
ceiving CPU until it is cleared. The pending request
is cleared when it causes an interruption and by CPU reset.