and zeros are stored in the interruption-code field.
In the EC mode, the instruction-length and interrup­
tion codes are not stored.
If the CPU is in the operating state, the exchange
of the PSW s occurs at the completion of the current
unit of operation and after all pending interruption
conditions for which the CPU is enabled have been
taken. In this case, it depends on the model if the CPU temporarily enters the stopped state as part of
the execution of the restart operation. If the CPU is
in the stopped state, the CPU enters the operating
state and exchanges the PSW s without first taking
any pending interruptions.
The restart interruption is initiated by activating
the restart key on the system console. In a multipro­
cessing system, the operation can also be initiated at
the addressed CPU by issuing SIGNAL PRO,­ CESSOR, specifying the restart order.
Programming Note
In order to perform restart when the CPU is in the
check-stop state, the CPU has to be reset. This can
be accomplished by means of program reset, which
does not clear the contents of program-addressable
registers, including the control registers, but causes
the attached channels to be reset.
Priority of Interruptions
During the execution of an instruction, several
interruption-causing events may occur simultaneous­
ly. The instruction may give rise to a program inter­
ruption, a request for an external interruption may
be received, equipment malfunctioning may be de­
tected, an I/O-interruption request may be made,
and the restart key may be activated. Instead of the
program interruption, a supervisor-call interruption
might occur; or both can occur if the program-event­
recording facility is installed. Simultaneous interrup­
tion requests are honored in a predetermined order.
An exigent machine-check condition has the high­
est priority. When it occurs, the current operation is
terminated or nullified. Program and supervisor-call
interruptions that would have occurred as a result of
the current operation may be eliminated. Any pend­
ing repressible machine-check conditions may be
indicated with the exigent machine-check interrup­
tion. Every reasonable attempt is made to limit the
side effects of an exigent machine-check condition,
and, normally, requests for I/O and external inter­
ruptions remain unaffected.
In the absence of an exigent machine-check con­
dition, requests for interruption existing concurrently
at the end of a unit of operation are honored in the Page ofGA22-7000-4
Revised September 1, 1975
By TNL: GN22-0498
following order of priority (the conditions are listed
in descending order of priorities):
Supervisor call
Program
Repressible machine-check
External
Input/ output
Restart
The processing of multiple simultaneous interrup­
tion requests consists in storing the old PSW and
fetching the new PSW belonging to the interruption
first taken. This new PSW is subsequently stored
without the execution of any instructions, and the
new PSW associated with the next interruption is
fetched. This storing and fetching continues until no
more interruptions are to be serviced. The priority is
reevaluated after the new PSW is loaded. Each eval­
uation is performed taking into consideration any ad­
ditional interruptions which may have become pend­
ing. Additionally, external and I/O interruptions, as
well as· machine-check interruptions due to repres-
sible conditions, are taken only if the current PSW at
the instant of evaluation indicates that the CPU is inter­
ruptible for the cause.
Instruction execution is resumed using the last­
fetched PSW. The order of executing interruption
subroutines is therefore the reverse of the order in
which the PSWs are fetched.
If the new PSW for a program interruption has an
unacceptable instruction address (the instruction
address is odd or causes an access exception to be
recognized), another program interruption occurs.
Since this second interruption introduces the same
unacceptable PSW, a string of interruptions is estab­
lished. These program exceptions are recognized as
part of the execution of the following instruction,
and the string may be broken by an I/O, external, or
restart interruption or the stop function.
If the new PSW for a program interruption con­
tains a one in an unassigned bit position in an EC­
mode PSW, or if it specifies the EC mode in a CPU that does not have the EC facility installed, or if it
specifies any other facility that is not installed on the
CPU, another program interruption occurs. This
condition is of higher priority than restart, I/O, ex­
ternal, or repressible machine-check conditions, or
the stop function, and CPU reset has to be used to
break the loop.
Interruption loops of other interruption classes
can also exist if the new PSW is enabled for the
same interruption. These include machine-check
interruptions and external interruptions due to
channel-available or PCI conditions. Interruption
loops involving more than one interruption class can
Interruptions 89
Page of GA22-7000-4
Revised September 1, 1975
By TNL: GN22-0498
also exist. For example, assume that the CPU timer
is negative and the CPU-timer subclass mask is one.
If the external new PSW has an exception which is
recognized as part of early recognition, and the pro­
gram new PSW is enabled for external interruptions,
then a series of interruptions occur, alternating be­
tween external and program. Even more complex
loops are possible. So long as more interruptions
must be serviced, the loop cannot be broken by em­
ploying the stop function; CPU reset is required. Similarly, CPU reset has to be invoked to termi­
nate the condition that exists when an interruption is
attempted with a prefix value designating a main­
storage location that is not available to the CPU. On some models, when an excessive number of consecutive interruptions is detected which cannot
be broken by means of the stop function, the CPU enters a special state that can be exited only by use
of CI)U reset.
Interruptions for all requests for which the CPU is
enabled are taken before the CPU is placed in the
stopped state. When the CPU is in the stopped state,
restart has a higher priority than pending I/O, exter­
nal, or repressible machine-check conditions. Progl'amming Note
The order in which concurrent interruption requests
are honored can be changed to some extent by
masking.
Assigned Main-Storage Locations Real' Main Storage
The chart "Assigned Locations in Real Main Stor­ age" shows the format and extent of the assigned
locations in real main storage. In a multiprocessing
system, real storage addresses are transformed to
absolute addresses by means of prefixing. The loca­
tions are used as follows. Unless specifically noted,
the usage applies to both the BC and EC modes. 0- 7 Restart New P S W: The new PSW is
fetched from locations 0-7 during the re.­
start interruption.
8-15 Restart Old PSW: The current PSW is
stored as the old PSW at locations 8-15
during the restart interruption. 24-63 64-71 Interruption Old PSWs: The current PSW is stored as the old PSW at locations
24-31, 32-39, 40-47, 48-55, and 56-63
during the external, supervisor-call, pro­
gram, machine-check, and input/output
interruptions, respectively. CSW: The channel status word (CSW) is
stored at locations 64-71 during an I/O 90 System/370 Principles of Operation
interruption. It, or portions thereof, may
be stored during the execution of START I/O, START I/O FAST RELEASE, TEST I/O, CLEAR I/O, HALT I/O, or
HALT DEVICE, in which case condition
code 1 is set.
72-75 CA W: The channel address word (CAW)
is fetched from locations 72-75 during
the execution of START I/O and START I/O FAST RELEASE. 80-83 Interval Timer: Locations 80-83 contain
the interval timer. The timer is updated
whenever the CPU is in the operating
state. Depending on the resolution of the
timer, the low-order locations may not be
updated.
88-127 Interruption New PSWs: The new PSW is fetched from locations 88-95, 96-103,
104-111, 112-119, and 120-127 during
the external, supervisor-call, program,
machine-check, and input/ output inter­
ruptions, respectively.
132-133 Processor Address: During an external
interruption due to malfunction alert,
emergency signal, or external call, the
processor address associated with the
source of the interruption is stored at lo­
cations 132-133. For all other external
interruption conditions, zeros are stored
at locations 132-133 when the old PSW specified EC mode, and the field remains
unchanged when the old PSW specified
the BC mode.
134-135 External-Interruption Code: During an
external interruption in the EC mode, the
interruption code is stored at locations
134-135.
136-139 Supervisor-Call-Interruption
Identification: During a supervisor-call
interruption in the EC mode, the
instruction-length code is stored in bit
positions 5 and 6 of location 137, and the
interruption code is stored at locations
138-139. Zeros are stored at location 136
and in the remaining bit positions of 137.
140-143 Program-Interruption Identification: Dur­
ing a program interruption in the EC
mode, the instruction-length code is
stored in bit positions 5 and 6 of location
141, and the interruption code is stored
at locations 142-143. Zeros are stored at
location 140 and in the remaining bit
positions of 141.
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