and zeros are stored in the interruption-code field.
In the EC mode, the instruction-length and interrup
tion codes are not stored.
If theCPU is in the operating state, the exchange
of thePSW s occurs at the completion of the current
unit of operation and after all pending interruption
conditions for which theCPU is enabled have been
taken. In this case, it depends on the model if theCPU temporarily enters the stopped state as part of
the execution of the restart operation. If theCPU is
in the stopped state, theCPU enters the operating
state and exchanges thePSW s without first taking
any pending interruptions.
The restart interruption is initiated by activating
the restart key on the system console. In a multipro
cessing system, the operation can also be initiated at
the addressedCPU by issuing SIGNAL PRO, CESSOR, specifying the restart order.
Programming Note
In order to perform restart when theCPU is in the
check-stop state, theCPU has to be reset. This can
be accomplished by means of program reset, which
does not clear the contents of program-addressable
registers, including the control registers, but causes
the attached channels to be reset.
Priority of Interruptions
During the execution of an instruction, several
interruption-causing events may occur simultaneous
ly. The instruction may give rise to a program inter
ruption, a request for an external interruption may
be received, equipment malfunctioning may be de
tected, an I/O-interruption request may be made,
and the restart key may be activated. Instead of the
program interruption, a supervisor-call interruption
might occur; or both can occur if the program-event
recording facility is installed. Simultaneous interrup
tion requests are honored in a predetermined order.
An exigent machine-check condition has the high
est priority. When it occurs, the current operation is
terminated or nullified. Program and supervisor-call
interruptions that would have occurred as a result of
the current operation may be eliminated. Any pend
ing repressible machine-check conditions may be
indicated with the exigent machine-check interrup
tion. Every reasonable attempt is made to limit the
side effects of an exigent machine-check condition,
and, normally, requests forI/O and external inter
ruptions remain unaffected.
In the absence of an exigent machine-check con
dition, requests for interruption existing concurrently
at the end of a unit of operation are honored in thePage ofGA22-7000-4
Revised September 1, 1975
By TNL: GN22-0498
following order of priority (the conditions are listed
in descending order of priorities):
Supervisor call
Program
Repressible machine-check
External
Input/ output
Restart
The processing of multiple simultaneous interrup
tion requests consists in storing the oldPSW and
fetching the newPSW belonging to the interruption
first taken. This newPSW is subsequently stored
without the execution of any instructions, and the
newPSW associated with the next interruption is
fetched. This storing and fetching continues until no
more interruptions are to beserviced. The priority is
reevaluated after the newPSW is loaded. Each eval
uation is performed taking into consideration any ad
ditional interruptions which may have become pend
ing. Additionally, external andI/O interruptions, as
well as· machine-check interruptions due to repres-
sible conditions, are taken only if the currentPSW at
the instant of evaluation indicates that theCPU is inter
ruptible for the cause.
Instruction execution is resumed using the last
fetchedPSW. The order of executing interruption
subroutines is therefore the reverse of the order in
which thePSWs are fetched.
If the newPSW for a program interruption has an
unacceptable instruction address (the instruction
address is odd or causes an access exception to be
recognized), another program interruption occurs.
Since this second interruption introduces the same
unacceptablePSW, a string of interruptions is estab
lished. These program exceptions are recognized as
part of the execution of the following instruction,
and the string may be broken by anI/O, external, or
restart interruption or the stop function.
If the newPSW for a program interruption con
tains a one in an unassigned bit position in an EC
modePSW, or if it specifies the EC mode in a CPU that does not have the EC facility installed, or if it
specifies any other facility that is not installed on the
CPU, another program interruption occurs. This
condition is of higher priority than restart,I/O, ex
ternal, or repressible machine-check conditions, or
the stop function, andCPU reset has to be used to
break the loop.
Interruption loops of other interruption classes
can also exist if the newPSW is enabled for the
same interruption. These include machine-check
interruptions and external interruptions due to
channel-available or PCI conditions. Interruption
loops involving more than one interruption class can
Interruptions 89
In the EC mode, the instruction-length and interrup
tion codes are not stored.
If the
of the
unit of operation and after all pending interruption
conditions for which the
taken. In this case, it depends on the model if the
the execution of the restart operation. If the
in the stopped state, the
state and exchanges the
any pending interruptions.
The restart interruption is initiated by activating
the restart key on the system console. In a multipro
cessing system, the operation can also be initiated at
the addressed
Programming Note
In order to perform restart when the
check-stop state, the
be accomplished by means of program reset, which
does not clear the contents of program-addressable
registers, including the control registers, but causes
the attached channels to be reset.
Priority of Interruptions
During the execution of an instruction, several
interruption-causing events may occur simultaneous
ly. The instruction may give rise to a program inter
ruption, a request for an external interruption may
be received, equipment malfunctioning may be de
tected, an I/O-interruption request may be made,
and the restart key may be activated. Instead of the
program interruption, a supervisor-call interruption
might occur; or both can occur if the program-event
recording facility is installed. Simultaneous interrup
tion requests are honored in a predetermined order.
An exigent machine-check condition has the high
est priority. When it occurs, the current operation is
terminated or nullified. Program and supervisor-call
interruptions that would have occurred as a result of
the current operation may be eliminated. Any pend
ing repressible machine-check conditions may be
indicated with the exigent machine-check interrup
tion. Every reasonable attempt is made to limit the
side effects of an exigent machine-check condition,
and, normally, requests for
ruptions remain unaffected.
In the absence of an exigent machine-check con
dition, requests for interruption existing concurrently
at the end of a unit of operation are honored in the
Revised September 1, 1975
By TNL: GN22-0498
following order of priority (the conditions are listed
in descending order of priorities):
Supervisor call
Program
Repressible machine-check
External
Input/ output
Restart
The processing of multiple simultaneous interrup
tion requests consists in storing the old
fetching the new
first taken. This new
without the execution of any instructions, and the
new
fetched. This storing and fetching continues until no
more interruptions are to be
reevaluated after the new
uation is performed taking into consideration any ad
ditional interruptions which may have become pend
ing. Additionally, external and
well as· machine-check interruptions due to repres-
sible conditions, are taken only if the current
the instant of evaluation indicates that the
ruptible for the cause.
Instruction execution is resumed using the last
fetched
subroutines is therefore the reverse of the order in
which the
If the new
unacceptable instruction address (the instruction
address is odd or causes an access exception to be
recognized), another program interruption occurs.
Since this second interruption introduces the same
unacceptable
lished. These program exceptions are recognized as
part of the execution of the following instruction,
and the string may be broken by an
restart interruption or the stop function.
If the new
tains a one in an unassigned bit position in an EC
mode
specifies any other facility that is not installed on the
CPU, another program interruption occurs. This
condition is of higher priority than restart,
ternal, or repressible machine-check conditions, or
the stop function, and
break the loop.
Interruption loops of other interruption classes
can also exist if the new
same interruption. These include machine-check
interruptions and external interruptions due to
channel-available or PCI conditions. Interruption
loops involving more than one interruption class can
Interruptions 89