Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 The relationship between, real and absolute ad­
dresses is graphically depicted in the figure
"Relationship Between Real and Absolute Addresses. " The prefix is a 12-bit quantity located in the pre-
fix register. The register has the following format: The contents of the register can be set and in­ specte:d by the privileged instructions SET PREFIX and STORE PREFIX, respectively. On setting, bits
corresponding to bit positions 0-7 and 20--31 of the
prefix register are ignored. On storing, zeros are
provided for these bit positions. The prefix register is initialiized to zero. PreJixing is applied to all references to main stor­
age and to keys in storage, except for references by
a CPU to the permanently assigned storage locations
during performance of the store-status function, and
except for references by a channel to extended­
logout locations, to 110 data, to indirect-data-
address words, and to CCWs. When dynamic ad­
dress translation is specified, prefixing is applied
after the address has been translated by the dynamic­
address-translation mechanism. When installed,
prefixing is always active and is not subject to any
mode control.
When prefixing is applied, the storage address is
translated as follows:
1. Bits 8-19 of the storage address, if all zeros,
are replaced with bits 8-19 of the prefix.
2. Bits 8-19 of the storage address, if equal to bits
8-19 of the prefix, are replaced with all zeros.
3. Bits 8-19 of the storage address, if not all zeros
and not equal to bits 8-19 of the prefix, remain
unchanged.
In all cases, bits 20-31 of the storage address re­
main unchanged.
Only the address presented to storage is translat­
ed by prefixing. The contents of the source of the
address remain unchanged.
The distinction between real and absolute ad­
dresses is made even when prefixing is not installed I I I Kf-----If-.No Change-r------+---- I I I CJ, I I I I I I /Address 4096 LAddress I \ ; I L __________ I Address I 4096 I L ________ -.J o Real Addresses
for CPU A Absolute Addresses CD Rlaal addresses in which the high·order 12 bits are equal to the prefix for this CPU (A or B). (3) Absolute addresses of the block that contains, for this CPU (A or B), the assigned locations in real storage.
Relationship Between Real and Absolute Addresses
96 System/370 Principles of Operation ...-Address 4096 ...-Address o Real Addresses
for CPU B

or when the prefix register contains all zeros. In both
of these cases, a real address and its corresponding
absolute address are identical. CPU Signaling and Response
The CPU-signaling-and-response facility provides
for communications among CPUs by means of the
SIGNAL PROCESSOR instruction. It provides for
transmitting and receiving the signal, decoding a set
of assigned order codes, performing the specified
operation, and responding to the signaling CPU. If a CPU has the CPU-signaling-and-response
facility installed, it can address the SIGNAL PRO­ CESSOR fnstruction to itself. All orders are executed
as defined. Orders Twelve orders are provided for communications
among CPUs in a multiprocessing system. The or­
ders are specified in bit positions 24-31 of the
second-operand address of SIGNAL PROCESSOR and are ericoded as follows:
Code Order 00 Invalid and Unassigned 01 Sense 02 External Call 03 Emergency Signal 04 Start 05 Stop 06 Restart 07 Initial Program Reset 08 Program Reset 09 Stop and Store Status OA Initial Microprogram Load 08 I nitial CPU Reset OC CPU Reset
OD-FF I nvalid and Unassigned
The orders are defined as follows:
Sense: The addressed CPU presents its status to the
issuing CPU (see "Status Bits" in this chapter for a
definition of the bits). No other action is caused at
the addressed CPU. The status, if not all zeros, is
stored in the general register designated by the Rl
field, and condition code 1 is set; if all status bits are
zero, condition code 0 is set.
External Call: An "external call" external­
interruption condition is generated at the addressed CPU. The interruption condition becomes pending
during the execution of the SIGNAL PROCESSOR instruction. The associated interruption occurs when
the CPU is interruptible for that condition and does
not necessarily occur during the execution of the
SIGNAL PROCESSOR instruction. The address of
the CPU sending the signal is provided with the in-
terruption code when the interruption occurs. Only one external-call condition can be kept pending in a CPU at a time.
Emergency Signal: An "emergency-signal" external­
interruption condition is generated at the addressed CPU. The interruption condition becomes pending
during the execution of the SIGNAL PROCESSOR instruction. The associated interruption occurs when
the CPU is interruptible for that condition and does
not necessarily occur during the execution of the
SIGNAL PROCESSOR instruction. The address of
the CPU sending the signal is provided with the in­
terruption code when the interruption occurs. At any
one time the receiving CPU can keep pending one
emergency-signal condition for each CPU of the
multiprocessing system, including the receiving CPU itself.
Start: The addressed CPU is placed in the operating stqte (see "Stopped and Operating States" in the
chapter "System Control"). The order is effective
only when the addressed CPU is in the stopped
state, and the effect is unpredictable when the stopped
state has been entered by reset. The CPU does
not necessarily enter the operating state during the
execution of the SIGNAL PROCESSOR instruction.
Stop: The addressed CPU performs the stop func­
tion (see "Stopped and Operating States" in the
chapter "System Control"). The CPU does not
necessarily enter the stopped state during the execu­
tion of the SlGNAL PROCESSOR instruction. No
action is caused at the addressed CPU if that CPU is
in the stopped state when the order code is accepted.
Restarl: The addressed CPU performs the restart
function (see "Restart" in the chapter "I . ") Th C . nterruptIons. e PU does not necessarily
perform the function during the execution of the
SIGNAL PROCESSOR instruction.
Initial Program Reset: The addressed CPU per­
forms initial program reset (see "Resets" in the
chapter "System Control"). The execution of the
reset does not affect other CPUs and does not affect
channels not configured to the CPU being reset. The
reset operation is not necessarily completed during
the execution of the SIGNAL PROCESSOR instruc­
tion.
Program Reset: The addressed CPU performs pro­
gram reset (see "Resets" in the chapter" System
Control"). The execution of the reset does not affect
other CPUs and does not affect channels not config-
Multiprocessing 97